公开(公告)号：EP1008170A1

公开(公告)日：2000-06-14

申请号：EP98911858.3

申请日：1998-03-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HAUSE, Frederick, N. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J. ,  MOORE, Bradley, T.

IPC: H01L21/265 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L21/3221 ,  Y10S148/024 ,  Y10S148/06

Abstract: Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.

公开(公告)号：EP0963606A1

公开(公告)日：1999-12-15

申请号：EP97907668.0

申请日：1997-02-18

Applicant: Advanced Micro Devices, Inc.

Inventor： FULFORD, H., Jim, Jr. ,  BANDYOPADHYAY, Basab ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21 ,  H01L23 ,  H01L27

CPC classification number: H01L23/5222 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

公开(公告)号：EP0943119A1

公开(公告)日：1999-09-22

申请号：EP97952347.0

申请日：1997-12-04

Applicant: Advanced Micro Devices, Inc.

Inventor： MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F1 ,  G03F7 ,  H01L21

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70241

Abstract: A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.