公开(公告)号：WO2003054966A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041102

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHAN, Darin, A. ,  EN, William, G. ,  PELLERIN, John, G. ,  MICHAEL, Mark, W.

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer (14) over an insulating layer (12), and partially removing a first portion of the silicon layer (14). The silicon layer (14) includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer (14) initially can have the same thickness. A semiconductor device is also disclosed.

Abstract translation: 制造半导体器件的方法包括在绝缘层（12）上设置硅半导体层（14），并部分去除硅层（14）的第一部分。 硅层（14）包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，硅层（14）的第一和第二部分最初可以具有相同的厚度。 还公开了一种半导体器件。

公开(公告)号：WO1997041597A1

公开(公告)日：1997-11-06

申请号：PCT/US1997003255

申请日：1997-03-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim ,  DAWSON, Robert ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/76229

Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

Abstract translation: 提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。 隔离过程导致在紧邻有源区域的场区域中形成沟槽。 然而，这个沟槽并不完全穿过田野区域。 通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。 因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。 虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。 其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。 在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

公开(公告)号：WO1997039479A1

公开(公告)日：1997-10-23

申请号：PCT/US1997002502

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BRENNAN, William, S. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  MICHAEL, Mark, W.

IPC: H01L21/3105

CPC classification number: H01L21/76819 ,  H01L21/31055 ,  H01L21/76229

Abstract: An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer. After etch removal predominantly at the higher elevational regions, the remaining fill dielectric upper surface is removed to a level commensurate with the upper surface of silicon mesas thereby producing separate field dielectrics interposed between silicon mesas. The field dielectrics, regardless of their lateral area, each have a substantially planar upper surface at or slightly below the adjoining silicon mesas. By producing planar field dielectric upper surfaces, various problems of non-planarity are removed from the thin films which are thereafter formed on the field dielectrics or between the field dielectrics and silicon mesas.

Abstract translation: 提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。 隔离过程导致间隔开的多个场电介质，其具有彼此基本上共面的上表面和相邻的硅台面上表面。 因此，隔离过程是与浅沟槽技术一起使用的平坦化工艺，其中将蚀刻增强离子转移到该电介质的上部高度区域的填充电介质中。 当经受后续蚀刻剂时，掺杂剂导致以比较低的高度区域更快的速率去除较高的高度区域。 因此，掺杂剂的选择性放置和蚀刻去除预先将填充电介质上表面全局地横跨整个晶片进行预处理。 在主要在较高的高度区域进行蚀刻去除之后，剩余的填充电介质上表面被去除到与硅台面的上表面相当的水平，从而产生介于硅台面之间的单独的场电介质。 场电介质，无论它们的横向面积如何，每个在相邻的硅台面处或稍低于相邻的硅台面处都具有基本平坦的上表面。 通过产生平面场电介质上表面，从形成在场电介质上或在场电介质和硅台面之间的薄膜中去除了非平面性的各种问题。

公开(公告)号：WO1997047039A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002509

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FULFORD, H., Jim, Jr. ,  BANDYOPADHYAY, Basab ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors (104) on one level are staggered with respect to conductors (106) on another level. In densely spaced interconnect areas, interposed conductors (104) are burried in intermetallic dielectric layer (103) drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects.

Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括几层导体，其中一层上的导体（104）相对于另一层上的导体（106）交错排列。 在密集间隔的互连区域中，插入的导体（104）被夹在金属间介电层（103）中，拉伸到不同的高度水平以减小互连之间的电容耦合。

公开(公告)号：WO1997047035A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002510

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MICHAEL, Mark, W. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  BRENNAN, William, S.

IPC: H01L21/768

CPC classification number: H01L21/0334 ,  H01L21/31051 ,  H01L21/76819

Abstract: A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational (dummy) conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

Abstract translation: 提供了一种光刻掩模衍生过程，用于改善由衍生的光刻掩模形成的导体上沉积的层间电介质的整体平面性。 导出光刻掩模，使得非操作（虚拟）导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，在该导体上介质层可以沉积并容易地使其平坦化，例如， 化学机械抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体因此不对集成电路功能有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

公开(公告)号：WO2008005083A1

公开(公告)日：2008-01-10

申请号：PCT/US2007/007842

申请日：2007-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  MICHAEL, Mark, W. ,  CHEN, Jian

Inventor： MICHAEL, Mark, W. ,  CHEN, Jian

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/823418 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method includes forming a plurality of functional features (210, 410) on a semiconductor layer (205, 405) in a first region. A non-functional feature (240, 415) corresponding to the functional feature (210, 410) is formed adjacent at least one of the functional features (210, 410) disposed on a periphery of the region. A stress- inducing layer (300, 500) is formed proximate the functional features (210, 410) and the non-functional feature (240, 415). A device (200, 400) includes a semiconductor layer (205, 405), a plurality of transistor elements (210, 410), a first dummy gate electrode (240A, 415A), and a stress-inducing layer (300, 500). The plurality of transistor elements (210, 410) is formed above the semiconductor layer (205, 405). The plurality includes at least a first end transistor element (210A, 410A), a second end transistor element (210D, 410C), and at least one interior transistor element (210B, 21 OC, 410B). The first dummy gate electrode (240A, 415A) is disposed proximate the first end transistor element (210A, 415A). The stress-inducing layer (300, 500) is disposed proximate the plurality of transistor elements (210, 410) and the first dummy gate electrode (240A, 415A).

Abstract translation: 一种方法包括在第一区域中的半导体层（205,405）上形成多个功能特征（210,410）。 对应于功能特征（210,410）的非功能特征（240,415）形成在邻近设置在区域外围的功能特征（210,410）中的至少一个功能特征（210,410）。 在功能特征（210,410）和非功能特征（240,415）附近形成应力诱导层（300,500）。 一种器件（200,400）包括半导体层（205,405），多个晶体管元件（210,410），第一伪栅电极（240A，415A）和应力诱导层（300,500） 。 多个晶体管元件（210,410）形成在半导体层（205,405）的上方。 多个至少包括第一端部晶体管元件（210A，410A），第二端部晶体管元件（210D，410C）和至少一个内部晶体管元件（210B，21C，410B）。 第一虚拟栅电极（240A，415A）设置在第一端部晶体管元件（210A，415A）附近。 应力诱导层（300,500）设置在多个晶体管元件（210,410）和第一伪栅电极（240A，415A）附近。

公开(公告)号：WO1998025182A1

公开(公告)日：1998-06-11

申请号：PCT/US1997022616

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70241

Abstract: A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

Abstract translation: 掩模版（130）提供图像图案并补偿光刻系统中的透镜误差。 使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。 通过调节辐射透射区域（132,134）的配置（或布局），例如通过调节石英基底的顶表面上的铬图案，可以对掩模版进行结构上的修改。 或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。 图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

公开(公告)号：WO1997047036A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002513

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/768 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors (12, 14), wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. The conductors and vias are made by a damascene process. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括多个级别的导体（12,14），其中一个层上的导体相对于另一层上的导体交错。 在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。 导体和通孔由镶嵌工艺制成。 通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

公开(公告)号：WO2007133342A1

公开(公告)日：2007-11-22

申请号：PCT/US2007/007575

申请日：2007-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  WU, David, D. ,  MICHAEL, Mark, W.

Inventor： WU, David, D. ,  MICHAEL, Mark, W.

IPC: H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/76819 ,  H01L21/76802 ,  H01L21/76834 ,  H01L29/7843

Abstract: The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature (20) above a semiconducting substrate (22), forming a layer stack comprised of a plurality of layers of material above the feature (22), the layer stack having an original height (32), reducing the original height (32) of the layer stack to thereby define a reduced height (32A) layer stack above the feature, forming an opening (38) in the reduced height layer (32A) stack for a conductive member (40) that will be electrically coupled to the feature (20) and forming the conductive member (40) in the opening (30) in the reduced height (32A) layer stack.

Abstract translation: 本发明涉及形成接触开口的方法。 在一个说明性实施例中，该方法包括在半导体衬底（22）上方形成特征（20），形成由特征（22）上方的多层材料构成的层叠层，层叠层具有原始高度（32 ），减小层堆叠的原始高度（32），从而在特征之上限定减小的高度（32A）层堆叠，在用于导电构件（40）的减小高度层（32A）堆叠中形成开口（38） 其将电耦合到特征（20）并且在减小的高度（32A）层叠中的开口（30）中形成导电构件（40）。

公开(公告)号：WO2003054948A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041105

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： QI, Wen-Jie ,  PELLERIN, John, G. ,  EN, William, G. ,  MICHAEL, Mark, W. ,  CHAN, Darin, A.

IPC: H01L21/31

CPC classification number: H01L29/6659 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/3185 ,  H01L29/6656

Abstract: A method of forming a semiconductor device provides a gate electrode (22) on a substrate (20) and forms a polysilicon reoxidation layer (26) over the substrate (20) and the gate electrode (22). A nitride layer (28) is deposited over the polysilicon reoxydation layer (26) and anisotropically etched. The etching stops on the polysilicon reoxidation layer (26), with nitride offset spacers (30) being formed on the gate electrode (22). The use of the polysilicon reoxidation layer (26) as an etch stop layer prevents the gouging of the silicon substrate (20) underneath the nitride layer (28), while allowing the offset spacers (30) to be formed.

Abstract translation: 形成半导体器件的方法在衬底（20）上提供栅电极（22）并在衬底（20）和栅电极（22）上形成多晶硅再氧化层（26）。 氮化物层（28）沉积在多晶硅再氧化层（26）上并各向异性蚀刻。 在多晶硅再氧化层（26）上停止蚀刻，在栅电极（22）上形成氮化物偏移间隔物（30）。 多晶硅再氧化层（26）作为蚀刻停止层的使用防止了氮化物层（28）下面的硅衬底（20）的刨削，同时允许形成偏移间隔物（30）。