公开(公告)号：US20250044844A1

公开(公告)日：2025-02-06

申请号：US18365783

申请日：2023-08-04

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Alexander Gendler ,  Daniel U. Becker ,  Saher Odeh ,  Ilya Granovsky ,  Lior Zimet

IPC: G06F1/26

Abstract: Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

公开(公告)号：US20240370371A1

公开(公告)日：2024-11-07

申请号：US18607128

申请日：2024-03-15

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  James Vash ,  Gaurav Garg ,  Sergio Kolor ,  Harshavardhan Kaushikkar ,  Ramesh B. Gunna ,  Steven R. Hutsell

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US12112113B2

公开(公告)日：2024-10-08

申请号：US17194003

申请日：2021-03-05

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Dany Davidov ,  Nir Leshem ,  Mark Pilip ,  Lior Zimet

IPC: G06F30/392 ,  G06F13/40 ,  G06F115/02

CPC classification number: G06F30/392 ,  G06F13/4068 ,  G06F2115/02

Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

公开(公告)号：US20240201766A1

公开(公告)日：2024-06-20

申请号：US18522324

申请日：2023-11-29

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Ami Schwartzman ,  Lior Zimet

IPC: G06F1/28

CPC classification number: G06F1/28

Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.

公开(公告)号：US20240103074A1

公开(公告)日：2024-03-28

申请号：US18471096

申请日：2023-09-20

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Lior Zimet

IPC: G01R31/317 ,  G01R31/319

CPC classification number: G01R31/31724 ,  G01R31/31721 ,  G01R31/31908

Abstract: A configurable computer system is disclosed. The computer system includes a set of processing blocks and a set of programmable registers. A given one of the programmable registers corresponds to at least one of the processing blocks. The computer system is configured to receive a harvesting command that writes a disable value to a group of the programmable registers corresponding to a group of the set of processing blocks to be disabled for a selected computing platform of a plurality of different computing platforms. One or more hardware circuits are configured to perform tasks after a given boot of the computer system, the more tasks utilizing circuitry in the group of the set of processing blocks. A power control circuit is configured to, after tasks have been performed, temporarily disable the group of the set of processing blocks, thereby configuring the computer system for the selected computing platform.

公开(公告)号：US20240085968A1

公开(公告)日：2024-03-14

申请号：US18175900

申请日：2023-02-28

Applicant: Apple Inc.

Inventor： Tzach Zemer ,  Lior Zimet ,  Sagi Lahav

IPC: G06F1/3206 ,  G06F1/08 ,  G06F1/3234 ,  H04W52/02

CPC classification number: G06F1/3206 ,  G06F1/08 ,  G06F1/3234 ,  H04W52/02

Abstract: A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.

公开(公告)号：US11899523B2

公开(公告)日：2024-02-13

申请号：US17933168

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3206

CPC classification number: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US20230239252A1

公开(公告)日：2023-07-27

申请号：US17868495

申请日：2022-07-19

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Lior Zimet ,  Opher D. KAHN ,  Eran Tamari ,  Tzach Zemer ,  Per H. Hammarlund

IPC: H04L49/25 ,  H04L47/10

CPC classification number: H04L49/25 ,  H04L47/39

Abstract: In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

公开(公告)号：US11693472B2

公开(公告)日：2023-07-04

申请号：US17676668

申请日：2022-02-21

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Doron Rajwan ,  Tal Kuzi ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/324 ,  G06F1/3206

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.

公开(公告)号：US11675722B2

公开(公告)日：2023-06-13

申请号：US17337805

申请日：2021-06-03

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg ,  Lior Zimet ,  Harshavardhan Kaushikkar ,  Steven Fishwick ,  Steven R. Hutsell ,  Shawn M. Fukami

IPC: G06F13/40 ,  G06F15/173

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17381

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.