公开(公告)号：US12159835B2

公开(公告)日：2024-12-03

申请号：US18339102

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L23/00

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20240387390A1

公开(公告)日：2024-11-21

申请号：US18671478

申请日：2024-05-22

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/18

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US12021035B2

公开(公告)日：2024-06-25

申请号：US17931343

申请日：2022-09-12

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L22/32 ,  H01L23/488 ,  H01L23/49838 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/58 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L22/34 ,  H01L24/06

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US20240105704A1

公开(公告)日：2024-03-28

申请号：US18458918

申请日：2023-08-30

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jiongxin Lu ,  Kunzhong Hu ,  Jun Zhai ,  Sanjay Dabral

IPC: H01L25/18 ,  G02B6/43 ,  H01L23/00

CPC classification number: H01L25/18 ,  G02B6/43 ,  H01L24/08 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/08145 ,  H01L2224/08225

Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets. A heat spreader may be bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding. The chiplets within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

公开(公告)号：US20240105626A1

公开(公告)日：2024-03-28

申请号：US18296587

申请日：2023-04-06

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  SivaChandra Jangam ,  Zhitao Cao

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49894 ,  H01L23/5383 ,  H01L28/40

Abstract: Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.

公开(公告)号：US20240039539A1

公开(公告)日：2024-02-01

申请号：US18481931

申请日：2023-10-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

CPC classification number: H03K19/1776 ,  G06F15/7807 ,  H01L23/3114 ,  H05K1/0298

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US20240014178A1

公开(公告)日：2024-01-11

申请号：US18348641

申请日：2023-07-07

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L21/78 ,  H01L22/32 ,  H01L23/481 ,  H01L23/60 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/95001 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/30205

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US11862557B2

公开(公告)日：2024-01-02

申请号：US17483535

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L21/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/58 ,  H01L21/66 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/585 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/78 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/30 ,  H01L24/32 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US11831312B2

公开(公告)日：2023-11-28

申请号：US17678962

申请日：2022-02-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

CPC classification number: H03K19/1776 ,  G06F15/7807 ,  H01L23/3114 ,  H05K1/0298

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US20230335494A1

公开(公告)日：2023-10-19

申请号：US18339102

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/5286 ,  H01L23/49816 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H05K1/111 ,  H05K1/181 ,  H01L24/16

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.