公开(公告)号：WO1994023427A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003657

申请日：1994-04-04

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEHRENS, Richard, T. ,  GLOVER, Neal ,  DUDLEY, Trent, O. ,  ARMSTRONG, Alan, J. ,  ZOOK, Christopher, P. ,  BLISS, William, G.

IPC: G11B05/09

CPC classification number: H03H17/06 ,  G11B5/09 ,  G11B20/10009 ,  H03H17/02

Abstract: A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter (378, 373, 375, 377, 390, 396, 451, 453, 455, 459) provides the two programmable delays using only one delay line (390). Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput.

Abstract translation: 用于补偿与从磁介质读取的数据产生的离散主脉冲的数据流相关联的离散次级脉冲形成的滤波器。 滤波器的脉冲响应包括具有侧补偿系数的中心系数，用于当输入信号与脉冲响应卷积时衰减次级脉冲。 补偿系数的幅度和延迟可编程，并进行自适应调整，以优化给定环境的脉冲响应。 在传统的FIR实施例中，使用两条延迟线来产生中心系数和侧面补偿系数之间的两个可编程延迟。 在优选实施例中，IIR滤波器（378,373,375,377,390,396,451,453,455,459）仅使用一个延迟线（390）提供两个可编程延迟。 同样在优选实施例中，数据流被交织成偶数和奇数数据流，并且由两个滤波器并行处理，以使吞吐量翻倍。

公开(公告)号：WO1994023369A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003168

申请日：1994-03-23

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ASSAR, Mahmud ,  NEMAZIE, Siamack ,  ESTAKHRI, Petro

IPC: G06F12/02

CPC classification number: G06F3/0601 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7211 ,  Y10S706/90

Abstract: A semiconductor mass storage system (100) and architecture can be substituted for a rotating hard disk. The system and architecture avoid an eras cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block (step 202-206) rather than over itself as hard disk would. Periodically, the mass storage will need to be cleaned up (step 204). Secondly, means are provied for evenly using all blocks in the mass storage (Fig. 7). These advantages are achieved through the use of several flags (200), a map to correlate a logical address of a block to a physical address of that block (308, 408) and a count register for each block. In particular, flags are provided for defective blocks (118), used blocks (112), old version of a block (104, 116), a count to determine the number of times a block has been erased and written and erase inhibit flag (200).

Abstract translation: 半导体大容量存储系统（100）和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了时间周期。 通过将更改的数据文件编程为空的大容量存储块（步骤202-206）而不是将硬盘本身作为自己编写，可以避免擦除周期。 定期地，大容量存储将需要被清理（步骤204）。 其次，为了均匀地使用大容量存储中的所有块证明了装置（图7）。 这些优点通过使用几个标志（200）来实现，地图将块的逻辑地址与该块（308,408）的物理地址和每个块的计数寄存器相关联。 特别地，为缺陷块（118），使用块（112），旧版本的块（104,116）提供标志，确定块被擦除的次数的计数和写入和擦除禁止标志（ 200）。

公开(公告)号：WO1994018773A1

公开(公告)日：1994-08-18

申请号：PCT/US1994001008

申请日：1994-01-27

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEHRENS, Richard, T. ,  DUDLEY, Trent ,  GLOVER, Neal

IPC: H04L27/08

CPC classification number: H03G3/001 ,  G11B20/10009 ,  H03G3/3036

Abstract: A mixed analog and digital gain control circuit (126) for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier (202) that receives the signal from a read/write recording head preamplifier (128). The output of the variable gain amplifier (202) is connected through a multiplexer (203) and equalizer (204) to an analog to digital converter (206) for converting the analog signal to digital sample values at control sampling times. A gain control circuit (330) receives the digital values and the output of a pulse detector (312) indicating when a pulse has occured. A gain error detector (802) within the gain control circuit (330) determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered (804) and sent through a digital to analog converter (212) and then through an exponentiating circuit (216). The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier (202).

Abstract translation: 一种用于控制模拟输入信号的振幅的混合模拟和数字增益控制电路（126）。 电路具有从读/写记录头前置放大器（128）接收信号的可变增益放大器（202）。 可变增益放大器（202）的输出通过多路复用器（203）和均衡器（204）连接到模数转换器（206），用于在控制采样时间将模拟信号转换为数字采样值。 增益控制电路（330）接收指示何时发生脉冲的数字值和脉冲检测器（312）的输出。 增益控制电路（330）内的增益误差检测器（802）确定每个检测脉冲幅度的误差量，该误差量被滤波（804）并通过数模转换器（212）发送，然后 通过取幂电路（216）。 指数电路的输出连接到可变增益放大器（202）的增益控制输入。

公开(公告)号：WO1993015541A1

公开(公告)日：1993-08-05

申请号：PCT/US1993001036

申请日：1993-02-04

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  PUAR, Deepraj, S.

IPC: H02H09/04

CPC classification number: H01L27/0248

Abstract: A circuit (400) is added to a complementary metal-oxide silicon integrated circuit to provide an intentional, non-reverse-biased VDD-to-VSS shunt path for transient currents such as electrostatic discharges. This circuit protects the IC from ESD damage by turning on before any other path, thus directing the ESD transient current away from easily damage structures. Specifically, the ESD transient current is steered from the VDD rail (102) to the VSS rail (101) through the on conduction of a P-channel transistor (P3) whose source and drain are connected to VDD and VSS respectively. The voltage on the gate of this transistor follows the VDD supply rail because it is driven by a delay network formed by a second transistor (P4) and a capacitor (C1). This VDD-tracking delay network turns the VDD-to-VSS transistor on during a transient and off during normal operation of the IC.

公开(公告)号：WO1990012389A1

公开(公告)日：1990-10-18

申请号：PCT/US1990001808

申请日：1990-04-04

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  PATIL, Suhas, S.

IPC: G09G05/00

CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G3/3629 ,  G09G3/3651 ,  G09G2310/0229 ,  G09G2340/0435

Abstract: A system for converting raster-image data in sequential frames from a single stream to a plurality K of streams suitable for controlling images on a raster imaging surface having said plurality K of different segments (Upper segment, Lower segment) includes the generation of a stream of raster data SO (Single Stream Data) representing information to be on a portion of one of the segments, the plurality K including the raster data stream SO; the generation of an additional plurality K-1 of streams of raster data; the delaying ( DELTA n/2 + DELTA n/2 + DELTA r) of each of said plurality K-1 of streams of raster data relative to the stream of raster data SO by different amounts which are functions of K and the number of lines (n) in a frame, and simultaneously supplying (gates 0, 1) one of the plurality of streams of raster data to each of the different segments of the imaging surface in the sequential order required to produce an image corresponding to SO on the imaging surface.

Abstract translation: 一种用于将顺序帧中的光栅图像数据从单个流转换为适合于控制具有所述多个不同片段（上段，下段）的光栅成像表面上的图像的多个流的系统包括：生成流 光栅数据SO（单流数据），其表示在一个片段的一部分上的信息，包括光栅数据流SO的多个K; 产生另外多个K-1个光栅数据流; 所述多个K-1光栅数据流中的每一个相对于光栅数据SO的延迟（DELTA n / 2 + DELTA n / 2 + DELTA r），其不同的量是K的函数和行数 （n），并且同时将所述多个光栅数据流中的一个栅极数据的一个供应到成像表面的每个不同段，以产生对应于成像上的SO的图像所需的顺序 表面。

公开(公告)号：WO1990012388A1

公开(公告)日：1990-10-18

申请号：PCT/US1990001877

申请日：1990-04-06

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BASSETTI, Chester, Floyd, Jr. ,  REDDY, Dayakar, Chandram ,  LAIMAN, Ekaputra ,  RICHTER, Bryan, Michel

IPC: G09G03/20

CPC classification number: H04N3/127 ,  G09G3/2003 ,  G09G3/2025 ,  G09G3/2051 ,  G09G3/2092 ,  G09G3/3611 ,  G09G2320/0247 ,  G09G2320/0261 ,  G09G2320/0266 ,  G09G2320/0276 ,  G09G2360/18

Abstract: The perpection of grayscale shading on a digitally commanded display (12) is produced by commanding pixels (12a) of the display with brightness-setting signals (0/17, 1/17, 2/17, ...17/17) of differing average duty cycles. The energization of spatially adjacent pixels (79, P1) is scattered in time and pixels which are energized at the same time (P0) are selected to be spatially scattered (78) so as to avoid the perception of visual disturbances such as flickering and surface streaming. This energization is represented as a placement pattern (77) which includes a previously energized pixel (P0) immediately surrounded by eight pixels (78) energigized at different phases and those eight pixels (78) are surrounded by pixels (79) which are preferred locations for the next pixel-energizing pulse. This pattern (77) is shifted throughout the matrix in correspondance with the movement of the previously energized pixel (P0).

Abstract translation: 通过用亮度设定信号（0/17，1/17，2/17，... 17/17）指示显示器的像素（12a）来产生数字指令显示器（12）上的灰度阴影， 不同的平均工作周期。 空间相邻像素（79，P1）的激励在时间上散射，同时被激励的像素（P0）被选择为在空间上散射（78），以避免视觉干扰（例如闪烁和表面）的感知 流。 该通电被表示为放置图案（77），其包括由在不同相位被加能的八个像素（78）紧紧包围的先前通电的像素（P0），并且那些八个像素（78）被作为优选位置的像素（79）包围 用于下一个像素激励脉冲。 与先前通电的像素（P0）的运动对应，该图案（77）在整个矩阵中移动。

公开(公告)号：WO1990012363A1

公开(公告)日：1990-10-18

申请号：PCT/US1990001952

申请日：1990-04-10

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BRIL, Vlad ,  HELLER, Paul, W., T. ,  UHLIN, Keith, H.

IPC: G06F09/24

CPC classification number: G06F12/0623 ,  G06F9/4486

Abstract: An addressing technique for transparently managing assignment of memory storage locations in a memory having a total capacity of T bytes for a computer operating system, the operating system having a number M of bytes of storage allocated thereto in the system memory map for storage of the operating system, involves assigning a number N of bytes of memory storage locations for storage of a core portion of the operating system, the number N being less than M, assigning a number S of blocks of additional memory storage locations in the memory, each of the S blocks of memory storage having a capacity of R bytes, where N+R=M; storing the portions of the operating system in addition to the core portion in the S number of blocks of the memory storage locations; retrieving one of the blocks S of the operating system from the memory storage; and retrieving the N number of bytes of the core portion of the operating system from memory storage, and utilizing the retrieved one of the blocks S with the retrieved number N of bytes of the core portion to produce the number M of bytes of the operating system.

公开(公告)号：WO2000004493A1

公开(公告)日：2000-01-27

申请号：PCT/US1999015014

申请日：1999-07-01

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  COUSINS, Robert, E. ,  SHAW, Steven, A.

IPC: G06T1/00

CPC classification number: H04N5/2258 ,  G06F15/02 ,  G06F15/0225 ,  H04N5/23229

Abstract: The present invention is a multi-purpose portable imaging device. The device is small enough to be hand-held or wearable and has embedded on its surface at least one sensor. These sensors may be active or passive. Analog energy received from the sensors is converted into a digital format and sent to an advanced computer. The computer is constructed on parallel architecture platform. The computer has the capability of taking data from multiple sensors and providing sensor fusion features. The data is processed and displayed in a graphical format in real time which is viewed on the imaging device. A keypad for entering data and commands is available on the device. The device has the capability of using a removable cartridge embedded with read only memory modules containing application software for manipulating data from the sensors. The application cartridge provides the imaging device with its multi-purpose functionality. Methods of utilizing expert systems to match generated images, or dielectric constants is provided.

Abstract translation: 本发明是一种多功能便携式成像装置。 该设备足够小，可以手持或可穿戴，并在其表面上嵌入至少一个传感器。 这些传感器可能是主动的或被动的。 从传感器接收的模拟能量被转换为数字格式并发送到高级计算机。 计算机构建在并行架构平台上。 计算机具有从多个传感器获取数据并提供传感器融合特征的能力。 数据以图像格式被实时处理和显示，其在成像设备上观看。 用于输入数据和命令的键盘可在设备上使用。 该设备具有使用嵌入有只读存储器模块的可移动盒带的能力，该存储器模块包含用于操纵来自传感器的数据的应用软件。 应用墨盒为成像设备提供其多功能功能。 提供了利用专家系统匹配生成的图像或介电常数的方法。

公开(公告)号：WO1998029980A2

公开(公告)日：1998-07-09

申请号：PCT/US1997024294

申请日：1997-12-24

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  GUPTA, Sanjay

IPC: H04L07/00

CPC classification number: H04L7/027 ,  H04L7/046 ,  H04L7/08

Abstract: A periodic training signal is transmitted over a communications channel from a transmitter to a receiver. At the receiver, a spectrum estimation module is used to measure the spectrum of a set of uncorrected samples of the periodic training signal. The spectrum estimate is available at a discrete frequency spacing of an integer fraction (L > 1) of the frequency spacing the set of samples of the periodic training signal. A timing offset estimation module is then used to measure the ppm offset between the local and remote crystals. The timing offset estimation module runs in parallel with the spectrum estimation module. The spectrum estimate is convolved with the DFT of a periodic ramp function and the result squared to product an error spectrum. The error spectrum represents the error induced by differences between timing in the transmitter and receiver clock. The error spectrum is subtracted from the estimated spectrum to produce a corrected spectrum. The corrected spectrum may be used to generate an SNR spectrum to characterize the communications channel.

Abstract translation: 周期性训练信号通过通信信道从发射机发射到接收机。 在接收机处，频谱估计模块用于测量周期性训练信号的一组未校正样本的频谱。 频谱估计可以以周期性训练信号的采样集合的频率间隔的整数分数（L> 1）的离散频率间隔获得。 然后使用定时偏移估计模块来测量本地和远程晶体之间的ppm偏移。 定时偏移估计模块与频谱估计模块并行运行。 频谱估计与周期性斜坡函数的DFT进行卷积，结果平方以产生误差谱。 误差谱表示由发射机和接收机时钟之间的定时差引起的误差。 从估计的频谱中减去误差谱，以产生校正的频谱。 可以使用校正的频谱来产生用于表征通信信道的SNR频谱。

公开(公告)号：WO1998029945A1

公开(公告)日：1998-07-09

申请号：PCT/US1997024128

申请日：1997-12-30

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEZZANT, Daniel, G. ,  CARCHOT, Joseph ,  RAMPRASAD, Rangarajan ,  SHETTY, Nagina, Naresh

IPC: H03K03/86

CPC classification number: H03K5/135 ,  H03K5/00006

Abstract: A clock frequency multiplier with a rise detector flip-flop connected to a series of buffers having interspersed parallel output taps connected to a binary to Gray converter for providing real time rise status indications. The parallel tap outputs are connected to first, second and third multiplexers, to produce first and second fall outputs and a second rise output. The multiplexers are controlled by first, second and third corresponding tap circuits having hexadecimal inputs from a Gray to hexadecimal converter connected to the output of the binary to Gray converter through a flip-flop clocked by a second rise of the input clock signal.

Abstract translation: 具有连接到一系列缓冲器的上升检测器触发器的时钟倍增器，其具有连接到二进制到灰度转换器的散布的并行输出抽头，用于提供实时上升状态指示。 并联抽头输出连接到第一，第二和第三复用器，以产生第一和第二下降输出和第二上升输出。 多路复用器由具有从灰度到十六进制转换器的十六进制输入的第一，第二和第三对应分接电路控制，所述十六进制输入通过由输入时钟信号的第二个上升时钟的触发器连接到二进制到格雷转换器的输出。