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53 records (took 0.027 seconds)

    31.
    发明专利
    未知

    公开(公告)号：DE69321996T2

    公开(公告)日：1999-05-12

    申请号：DE69321996

    申请日：1993-06-14

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  CINATO PAOLA ,  DE BOSIO ALFREDO

    IPC: H04Q3/52 ,  H04L12/56 ,  H04Q11/00 ,  H04Q11/04

    Abstract: The optical switch for fast cell-switching networks comprises an optical interconnection network (CM) and an electrical control network (CT). In order to fully exploit optical component capabilities and to overcome the constraints imposed by operating speed limits of electronic components, each input (IN1...INk) of the interconnection network (CM) is associated with means (PAC1...PACk) forming aggregates of cells which are to follow a same path through the interconnection network and time-compressing the aggregates, and each output (OU1...OUk) is associated with means (PAD1...PADk) for the time expansion of the aggregates and separation of the aggregate cells.

    32.
    发明专利
    未知

    公开(公告)号：IT1285852B1

    公开(公告)日：1998-06-24

    申请号：ITTO960326

    申请日：1996-04-24

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  BURZIO MARCO ,  PELLEGRINO PAOLO ,  PESANDO LUCA

    IPC: H01L27/092 ,  H01L21/8238 ,  H01S5/042 ,  H01S5/068 ,  H01S5/40 ,  H04B10/04 ,  H04B10/06 ,  H04B10/142 ,  H04B10/152

    Abstract: The circuit comprises bias and modulation current generators (T1...T6) for both p-type and n-type optical sources, and a pair of sources of control voltages (B, M) for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic (LC) and CMOS gates (P1...P6), the generators required by the source (LA). The circuit is made by using three pads of an integrated circuit, one for each control voltage source (B, M) and the third (D) comprising the current generators (T1...T6), the CMOS gates (P1...P6) and the control logic (LC).

    DEVICE FOR AND METHOD OF ALIGNING IN TIME DIGITAL SIGNALS, FOR EXAMPLE A CLOCK SIGNAL AND A DATA STREAM
    34.
    发明专利
    DEVICE FOR AND METHOD OF ALIGNING IN TIME DIGITAL SIGNALS, FOR EXAMPLE A CLOCK SIGNAL AND A DATA STREAM 未知

    公开(公告)号：CA2212292A1

    公开(公告)日：1998-01-31

    申请号：CA2212292

    申请日：1997-07-30

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： PELLEGRINO PAOLO ,  BOSTICA BRUNO ,  BURZIO MARCO

    IPC: G06F13/42 ,  H03K5/00 ,  H03K5/13 ,  H04L7/02 ,  H04L7/033

    Abstract: A device and a method for aligning in time two essentially isochronous digit al signals are provided, in which a plurality (2n) of replicas (CK1-CK4) of the first s ignal (CKIN), separated by a given phase difference, are generated and a number of said re plicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of lo gic signals (SL0, SL1) is obtained which is representative of the phase relation existin g between each of said replicas (CK1-CK4) and the second signal (DATA). The output sig nal (CKOUT) of the device, aligned with the second signal, corresponds to the on e, among the replicas (CK1-CK4) of the first signal, which best reproduces the desire d alignment condition.

    35.
    发明专利
    未知

    公开(公告)号：ITTO960326A1

    公开(公告)日：1997-10-24

    申请号：ITTO960326

    申请日：1996-04-24

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  BURZIO MARCO ,  PELLEGRINO PAOLO ,  PESANDO LUCA

    IPC: H01L27/092 ,  H01L21/8238 ,  H01S5/042 ,  H01S5/068 ,  H01S5/40 ,  H04B10/04 ,  H04B10/06 ,  H04B10/142 ,  H04B10/152

    Abstract: The circuit comprises bias and modulation current generators (T1...T6) for both p-type and n-type optical sources, and a pair of sources of control voltages (B, M) for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic (LC) and CMOS gates (P1...P6), the generators required by the source (LA). The circuit is made by using three pads of an integrated circuit, one for each control voltage source (B, M) and the third (D) comprising the current generators (T1...T6), the CMOS gates (P1...P6) and the control logic (LC).

    37.
    发明专利
    未知

    公开(公告)号：ITTO940241D0

    公开(公告)日：1994-03-31

    申请号：ITTO940241

    申请日：1994-03-31

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  CINATO PAOLA ,  ZUCCHELLI LIBERO

    IPC: H04B10/02 ,  H04L7/00 ,  H04L7/04 ,  H04L12/56 ,  H04Q3/00

    Abstract: The device for the phase realignment of ATM cells in an optical ATM switching node is associated with each input line (Fe) of node and includes means (RIC) for recognizing the beginning of a cell, means (VE) for evaluating the time shift between of a cell and a reference instant and for generating an error signal (ER) depending on the amount of time difference, and means (LR) for compensating the time difference, driven by the error signal (ER). The time difference compensating means (LR) includes a logarithmic optical delay line that is connected upstream of the means (RIC, VE) for recognizing the beginning of a cell and for evaluating the amount of the time difference.

    39.
    发明专利
    未知

    公开(公告)号：DK155480C

    公开(公告)日：1989-09-18

    申请号：DK208681

    申请日：1981-05-12

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELFORTE PIERO ,  BOSTICA BRUNO ,  PILATI LUCIANO

    IPC: H04Q3/52 ,  H04Q11/04 ,  H04Q11/08

    Abstract: The present PCM switching element is intended to be used in digital telephone exchanges for the making of switching or concentration stages of whatever capacity. … In fact, structures consisting of a plurality of such elements are easily performed thanks to use of a bit associated with each outgoing PCM channel, called "busy bit". … The switching element can be controlled by a commercially available microprocessor and can be made as an integrated circuit.

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