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公开(公告)号：NO891581A
公开(公告)日：1989-11-27
申请号：NO891581
申请日：1989-04-18
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD
IPC: G11C11/401 , G11C7/10 , G06F12/06 , G06F13/10
CPC classification number: G11C7/1021
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公开(公告)号：DK189889A
公开(公告)日：1989-11-27
申请号：DK189889
申请日：1989-04-19
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , BLAND PATRICK MAURICE , DEAN MARK EDWARD
Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.
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公开(公告)号：DK189789A
公开(公告)日：1989-11-27
申请号：DK189789
申请日：1989-04-19
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , BLAND PATRICK MAURICE , DEAN MARK EDWARD
Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.
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公开(公告)号：DK189489A
公开(公告)日：1989-11-27
申请号：DK189489
申请日：1989-04-19
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , BLAND PATRICK MAURICE , DEAN MARK EDWARD
Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.
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公开(公告)号：DK189689D0
公开(公告)日：1989-04-19
申请号：DK189689
申请日：1989-04-19
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , BLAND PATRICK MAURICE , DEAN MARK EDWARD
Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.
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Patent Agency Ranking
公开(公告)号：FI891788A0
公开(公告)日：1989-04-14
申请号：FI891788
申请日：1989-04-14
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , DEAN MARK EDWARD , BLAND PATRICK MAURICE
Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.
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公开(公告)号：MX155926A
公开(公告)日：1988-05-23
申请号：MX20228784
申请日：1984-08-07
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , BOLT WILLIAM HAWKINS
Abstract: In a self-contained battery powered key entry device, the keyboard (2) is driven from a microprocessor (1) and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter (24). The sense lines (DBO-DB7) are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode. A delay may be incorporated.
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38.发明专利
公开(公告)号：GB2144889A
公开(公告)日：1985-03-13
申请号：GB8416920
申请日：1984-07-03
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , BOLT WILLIAM HAWKINS
Abstract: In a self-contained battery powered key entry device, the keyboard (2) is driven from a microprocessor (1) and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter (24). The sense lines (DBO-DB7) are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode. A delay may be incorporated.
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公开(公告)号：DE69423056T2
公开(公告)日：2000-09-14
申请号：DE69423056
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.
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公开(公告)号：DE69423056D1
公开(公告)日：2000-03-30
申请号：DE69423056
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.
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