公开(公告)号：SG191104A1

公开(公告)日：2013-07-31

申请号：SG2013044961

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

Abstract: On-the-Fly Compensation of Sampling Frequency and Phase Offset in Receiver Performing Ultra-High-Speed Wireless CommunicationAbstractThe present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.Fig. 4

公开(公告)号：DE112010004607B4

公开(公告)日：2014-12-18

申请号：DE112010004607

申请日：2010-11-05

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  NEGISHI YASUSHI ,  OKAZAKI ATSUYA

IPC: H04W40/34 ,  H04B7/10 ,  H04J99/00 ,  H04W16/28 ,  H04W84/18

Abstract: Paket-Datenübertragungssystem zum Synchronisieren der Übertragungszeitpunkte von Paketen zum Senden eines Pakets zu einer Zieladresse, wobei das System mehrere Knoten (100–190) umfasst, die eine Funk-Datenübertragung ausführen durch Senden und Empfangen von Funkwellen, die durch Steuern ihrer Phase eine bestimmte Richtungscharakteristik aufweisen, wobei jeder der Knoten (100–190) – im voraus festgelegte Weglenkungsinformationen verwendet zum Bestimmen eines Übertragungswegs eines Pakets, so dass alle Knoten eine oder mehrere geschlossene Schleifen bilden, – auf diesem Übertragungsweg ein Paket zu einem Übertragungszielknoten sendet und von einem Übertragungsquellenknoten empfängt, und – die in dem Paket enthaltene Zieladresse liest und das Paket an den Übertragungszielknoten durchleitet, bevor der Empfang des Pakets abgeschlossen wurde, und das Paket-Datenübertragungssystem – eine zeitliche Synchronisation durch Senden und Empfangen der Pakete während einer bestimmten Zeitperiode ausführt, – wobei zu einem Zeitpunkt, der von der bestimmten Zeitperiode verschieden ist, Weglenkungsinformationen in Übereinstimmung mit den Informationen der Pakete aktualisiert werden, die nach der zeitlichen Synchronisation von den Knoten gemeinsam genutzt werden, und jedem der Knoten ein Zeitrahmen als ein Zeitpunkt zugewiesen wird, an dem jeder Knoten ein Paket senden und empfangen darf.

公开(公告)号：AU2012227102A1

公开(公告)日：2013-10-10

申请号：AU2012227102

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

Abstract: The present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.

公开(公告)号：GB2488502A

公开(公告)日：2012-08-29

申请号：GB201211306

申请日：2010-11-05

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  NEGISHI YASUSHI ,  OKAZAKI ATSUYA

IPC: H04W40/02 ,  H04J3/06 ,  H04L12/56 ,  H04W40/06

Abstract: Disclosed is a system that enables efficient packet communication by exclusively transmitting and receiving a plurality of packets in space-time. Also disclosed is a communication method therefor. The system is provided with a plurality of nodes (100 to 190) that perform wireless communication, wherein the nodes store routing information, transmit and receive packets with directivity to and from transfer origin and transfer destination nodes upon a transmission path determined from the routing information by controlling the phase of the transmitted and received waves, and perform cut-through transmission. In the system, the phase of the transmitted and received waves is controlled during a given length of time in a manner such that all nodes form at least one closed loop, and time synchronization and the transmission and reception of packet communication history are performed by means of cut-through transmission. During all other time periods, the nodes transmit and receive packets in accordance with the routing information from the nodes that is updated on the basis of the time-synchronized packet communication history shared between nodes, and in accordance with the time frame in which the transmission and reception of packets that have been distributed to the nodes is possible.

公开(公告)号：AT211295T

公开(公告)日：2002-01-15

申请号：AT96300716

申请日：1996-02-01

Applicant: IBM

Inventor： KATAYAMA YASUNAO

IPC: G11C11/34 ,  G11C11/38 ,  H01L27/10 ,  H01L29/06

Abstract: A memory cell comprises at least three conducting layers (20) spaced with insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunnelling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunnelling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made. This provides a storage method of a static memory using a quantum device and a structure therefor. A memory cell according to the present invention has a structure simpler than static memories being presently used. Also, an area that this structure is substantially equal to the cell area of a DRAM. Further, since the circuit is complementary, a standby current can greatly be reduced.

公开(公告)号：DE69125542T2

公开(公告)日：1997-09-25

申请号：DE69125542

申请日：1991-07-26

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  SCHEUERLEIN ROY E

IPC: G11C11/409 ,  G11C11/4091

Abstract: A dynamic random access memory comprises a sense amplifier including a latch (10) comprising a pair of NMOS FETs (TN1,TN2) with their gates and drains cross coupled and with their sources connected to a common node. A pair of bitlines (BL,BLN) are coupled to the cross coupled nodes of the latch (10). An FET (TP5) enables the bitlines to be precharged to a precharge voltage. A latch driving circuit (16) is coupled to the common node of the latch (10). The latch driving circuit (16) comprises means (TN5,TN6) for coupling a reference voltage to the common node for activating the latch (10) after the bitlines have been precharged, and means (TN7,20) for controlling the voltage of the common node in such a manner that the downward voltage swing of the lower level bitline towards the reference voltage, produced by activation of the latch (10), is limited to a predetermined voltage level higher than the reference voltage. This advantageously provides a high speed memory operation and reduced power consumption.

公开(公告)号：CA2821227C

公开(公告)日：2019-03-05

申请号：CA2821227

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

Abstract: Problem To restore data in a transmitted symbol sequence without aligning the clock of the receiver with the clock of the transmitter. Solution Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner. In this configuration, a resampling filter circuit, an equalization filter circuit and a decimation filter circuit are realized in a single compensation filter circuit, which is much smaller than the prior art circuits in terms of size.

公开(公告)号：GB2488502B

公开(公告)日：2013-10-09

申请号：GB201211306

申请日：2010-11-05

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  NEGISHI YASUSHI ,  OKAZAKI ATSUYA

IPC: H04W40/02 ,  H04J3/06 ,  H04W40/06

公开(公告)号：DE112010004607T5

公开(公告)日：2013-01-24

申请号：DE112010004607

申请日：2010-11-05

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  NEGISHI YASUSHI ,  OKAZAKI ATSUYA

IPC: H04W40/34 ,  H04B7/10 ,  H04J99/00 ,  H04W16/28 ,  H04W84/18

Abstract: Es werden ein System und ein Datenübertragungsverfahren bereitgestellt, die eine wirksame Paket-Datenübertragung ermöglichen, indem mehrere Pakete exklusiv in Zeit und Raum gesendet und empfangen werden. Das System enthält mehrere Knoten, die eine Funk-Datenübertragung ausführen. Jeder Knoten speichert Weglenkungsinformationen und bestimmt einen Übertragungsweg durch die Verwendung der Weglenkungsinformationen und führt eine Durchleitungsübertragung aus, indem Pakete auf dem festgelegten Übertragungsweg zu einem Übertragungszielknoten gesendet und von einem Übertragungsquellenknoten empfangen werden durch das Senden und Empfangen von Funkwellen, denen jeweils durch Steuern ihrer Phasen eine bestimmte Richtungscharakteristik verliehen wird. n und das Senden und Empfangen von Paket-Datenübertragungsdatensätzen während einer bestimmten Zeitdauer durch Ausführen der Durchleitungsübertragung ausgeführt, während die Phasen der Sende- und Empfangsfunkwellen gesteuert werden, sodass alle Knoten eine oder mehrere geschlossene Schleifen bilden. Zu einem Zeitpunkt, der von der bestimmten Zeitdauer verschieden ist, sendet und empfängt der Knoten Pakete in Übereinstimmung mit den Weglenkungsinformationen und einem Zeitrahmen, der jedem der Knoten als ein Zeitpunkt zugeordnet ist, an dem jeder Knoten ein Paket senden und empfangen darf, wobei die Weglenkungsinformationen in jedem der Knoten gehalten werden und auf der Grundlage der Paket-Datenübertragungsdatensätze, deren Informationen nach der zeitlichen Synchronisation von den Knoten gemeinsam genutzt werden, aktualisiert werden.

公开(公告)号：CA2821227A1

公开(公告)日：2012-09-13

申请号：CA2821227

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

Abstract: The present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.