公开(公告)号：EP2672633A4

公开(公告)日：2014-03-26

申请号：EP12754784

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

CPC classification number: H04L27/01 ,  H04L7/0029 ,  H04L7/10 ,  H04L25/03038 ,  H04L27/22 ,  H04L27/38 ,  H04L2025/03471 ,  H04L2025/03605 ,  H04L2025/03687

公开(公告)号：AU2012227102B2

公开(公告)日：2015-11-19

申请号：AU2012227102

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

Abstract: The present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.

公开(公告)号：AU2012227102A1

公开(公告)日：2013-10-10

申请号：AU2012227102

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

Abstract: The present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.

公开(公告)号：DE112018003756T5

公开(公告)日：2020-04-16

申请号：DE112018003756

申请日：2018-09-28

Applicant: IBM

Inventor： MUNETOH SEIJI ,  SUBRAMANIAN CHITRA ,  HORIBE AKIHIRO ,  SUEOKA KUNIAKI ,  KOHDA YASUTERU

IPC: H01L21/66

Abstract: Ein Chip-Zwischenkörper weist einen Halbleiterbereich auf, der mehrere Chip-Bereiche enthält. Die Chip-Bereiche sind jeweils als Halbleiterchips herausgeschnitten. Ein Schneidebereich ist entlang von Rändern der Chip-Bereiche bereitgestellt, wobei der Schneidebereich geschnitten wird, um die Halbleiterchips herauszuschneiden. Ein Kontaktbereich ist über den Schneidebereich hinweg den Chip-Bereichen gegenüberliegend bereitgestellt, wobei der Kontaktbereich konfiguriert ist, von einer Prüfspitze einer Prüfeinheit kontaktiert zu werden, um die Chip-Bereiche zu prüfen, und wobei eine elektrische Verdrahtung durchgehend mit dem Schneidebereich bereitgestellt ist, um die Chip-Bereiche und den Kontaktbereich zu verbinden.

公开(公告)号：CA2821227C

公开(公告)日：2019-03-05

申请号：CA2821227

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

Abstract: Problem To restore data in a transmitted symbol sequence without aligning the clock of the receiver with the clock of the transmitter. Solution Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner. In this configuration, a resampling filter circuit, an equalization filter circuit and a decimation filter circuit are realized in a single compensation filter circuit, which is much smaller than the prior art circuits in terms of size.

公开(公告)号：CA2821227A1

公开(公告)日：2012-09-13

申请号：CA2821227

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

Abstract: The present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.

公开(公告)号：SG10201405464SA

公开(公告)日：2014-10-30

申请号：SG10201405464S

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

Abstract: Problem To restore data in a transmitted symbol sequence without aligning the clock of the receiver with the clock of the transmitter. Solution Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner. In this configuration, a resampling filter circuit, an equalization filter circuit and a decimation filter circuit are realized in a single compensation filter circuit, which is much smaller than the prior art circuits in terms of size.

公开(公告)号：SG191104A1

公开(公告)日：2013-07-31

申请号：SG2013044961

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

Abstract: On-the-Fly Compensation of Sampling Frequency and Phase Offset in Receiver Performing Ultra-High-Speed Wireless CommunicationAbstractThe present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.Fig. 4