公开(公告)号：GB2514395A

公开(公告)日：2014-11-26

申请号：GB201309265

申请日：2013-05-23

Applicant: IBM

Inventor： MICHEL PATRICK ,  OUAZANA CHRISTIAN ,  BENAYOUN ALAIN ,  FAUH JEAN-FRANCOIS ,  GOMEZ CLAUDE

IPC: G06F11/32

Abstract: A fault display module 205 for a hardware device such as a blade computer 102 comprises a first power input 211 for receiving power from a first power supply 104 for the hardware device, an input interface 206 for receiving fault data from the hardware device, non-volatile data storage 207 for storing the fault data, an output interface 208 for outputting the fault data to a display device 209 and an external power input 213 for providing power to the fault display module from a second power supply external to the hardware device when the associated hardware device is disconnected from the first power supply.

公开(公告)号：FR2805686B1

公开(公告)日：2004-11-12

申请号：FR0014653

申请日：2000-11-14

Applicant: IBM

Inventor： MICHEL PATRICK ,  OUAZANA CHRISTIAN ,  SERGENT BERNARD ,  VERHAEGHE MICHEL

IPC: H04L25/02 ,  H04L25/03 ,  H04L25/10 ,  H04B3/00 ,  H03H7/00 ,  H04B1/16 ,  H04L25/00

公开(公告)号：CA2413420A1

公开(公告)日：2002-01-24

申请号：CA2413420

申请日：2001-06-26

Applicant: IBM

Inventor： TOUBOL GILLES ,  BENAYOUN ALAIN ,  MICHEL PATRICK

IPC: G06F13/10 ,  G06F3/0354 ,  G06F3/038 ,  G06F3/033

Abstract: A system for establishing wireless connection between a peripheral device an d an intelligent device in a multi-computers environment having a plurality of intelligent devices, is disclosed. The system is in part included within the peripheral device which is preferably a mouse device and also is included within the intelligent device which is preferably a computer system. Specifi c routines of the system allow a user to work with any of the intelligent devices using only the one mouse device.

公开(公告)号：FR2803709A1

公开(公告)日：2001-07-13

申请号：FR0014655

申请日：2000-11-14

Applicant: IBM

Inventor： BENAYOUN ALAIN ,  MICHEL PATRICK ,  LE PENNEC JEAN FRANCOIS ,  TOUBOL GILLES

IPC: H04M11/06 ,  H04M3/56

Abstract: The assymetric digital subscriber line dynamic inversion system has central equipment (12) connected to a service network (10) with client equipment (26) connected to a client work post (32). The equipments are connected by a public telephone connection line (22). When high speed transmission is wanted a message inversion demand is set, activating the coding and decoding of the central equipment coding at a medium speed and decoding at a high speed. A message of reception is sent to the client equipment, activating coding and decoding at high speed in the client equipment, and transmitting a reception message back to the central equipment.

公开(公告)号：DE69326935T2

公开(公告)日：2000-05-18

申请号：DE69326935

申请日：1993-03-02

Applicant: IBM

Inventor： LE PENNEC JEAN-FRANCOIS ,  MICHEL PATRICK ,  SICSIC PATRICK ,  SPATARI JOSEPH

IPC: H04J3/00 ,  H04J3/22 ,  H04L12/20 ,  H04L25/14 ,  H04L69/14 ,  H04M3/00 ,  H04Q11/04

Abstract: The method involves the steps of establishing on request of a first DTE to a second remote DTE a set of n independent digital communication channels between said terminal adapters, and determining during an initialization phase the relationship between the slot of each channel used for the building of said aggregation superchannel and the chronologic order of the establishment of the considered slot. Then, the high-rate data flow is splitted and each byte is transmitted through the independent digital channels in accordance with the chronologic order which was previously assigned to each of the said channels. In the remote DTE, each byte of the splitted high-rate data flow are received through the different independent digital channels and are loaded in a single memory at an address which is computed from the following formula: A(n)= A(n-1) + n Where A(n-1) corresponds to the address in which is stored the preceding byte conveyed through the considered channel, and n corresponds to the number of digital channels established. Therefore, each channel works independently and there is no need to measure any delay between the channels. The memory storage will contain at continuous addresses the high-rate data flow. Applied to a ISDN, fractional T1 or multi-channel E1, the method provides an aggregate link operating a nx64 kpbs.

公开(公告)号：CA2105353C

公开(公告)日：1999-03-30

申请号：CA2105353

申请日：1993-09-01

Applicant: IBM

Inventor： AVARGUES DIDIER ,  CLARA JEAN-LOUIS ,  LE PENNEC JEAN-FRANCOIS ,  MICHEL PATRICK ,  SICSIC PATRICK

IPC: H04M11/00 ,  G06F15/177 ,  H04Q11/04 ,  H04L12/52

Abstract: A method for initializing ISDN adapter cards installed within a workstation having a main processor and an ISDN primary adapter for connecting the ISDN adapter cards to an ISDN primary gateway. Each ISDN adapter card has circuits for handling at least one B-channel, and a first processor associated with memory storage. The ISDN primary adapter includes a second processor associated with a second memory storage. In response to the reception of a specific polling pattern transmitted to each adapter card by the primary adapter, a pattern is transmitted to the workstation processor for requesting the loading of the second memory storage with operational code transferred from the workstation to the ISDN adapter card. The ISDN primary adapter, in response to the request pattern received by the main processor, transmits a second pattern via the ISDN adapter card that transmitted the first pattern, so that the main processor in the workstation and the processor in the ISDN primary adapter recognize the ISDN adapter card that transmitted the patterns to the workstation and to the ISDN primary adapter as the master ISDN adapter card for transmission of control information on the D-channel.

公开(公告)号：DE69124743D1

公开(公告)日：1997-03-27

申请号：DE69124743

申请日：1991-11-29

Applicant: IBM

Inventor： BARDET GERARD ,  LE PENNEC JEAN-FRANCOIS ,  MICHEL PATRICK ,  THERIAS PHILIPPE

IPC: H04L29/02 ,  H04L1/00 ,  H04L12/56 ,  H04L13/08 ,  H04L29/08

Abstract: A store and forward mechanism for telecommunication equipments including means (300) for deserializing a HDLC frame of data which is received from a first telecommunication node into a sequence of n-bits words. The frame includes a header, a data field and a frame checking sequence (FCS) generated by said first telecommunication node. The apparatus further includes processing means for generating n-bit words corresponding to a new header of said received HDLC frame. The store and forward apparatus comprises serializing means (600) receiving said processed n-bits words from said storage for generating a new HDLC frame comprising said new header field and a corresponding new FCS which is to be transmitted to said second telecommunication node. The apparatus further includes means (500) receiving the received HDLC frame simultaneously to the deserializing means and which computes a first partial FCS covering the data field only of the HDLC frame, and means (200) for storing that partial FCS. During the forward phase, the n-bits words which are to be transmitted to the next telecommunication node are simultaneously received by the HDLC serializer and by means (800) for computing a second partial FCS covering said data field only. At the end of the serialization process of the data field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line. Since the computing of both the first and second partial FCS is respectively performed during the deserializing of the HDLC frame and the serializing of the processed n-bit data words, no extra delay is required. The integrity of data during its storage in RAM is therefore provided without needed additional processing resources since the processor which is included within the store and forward mechanism has its resources which remain fully allocated for the store and forward process.

公开(公告)号：BR9304866A

公开(公告)日：1994-05-24

申请号：BR9304866

申请日：1993-11-29

Applicant: IBM

Inventor： AVARGUES DIDIER ,  CLARA JEAN-LOUIS ,  PENNEC JEAN-FRANCOIS LE ,  MICHEL PATRICK ,  SICSIC PATRICK

IPC: H04M11/00 ,  G06F15/177 ,  H04Q11/04 ,  G06F13/00

Abstract: Method for initializing a set of at least two ISDN adapter cards (210-240) being plugged within a workstation including a main processor and an ISDN primary adapter (222) for allowing the connection of said ISDN adapter cards (210-240) to an ISDN primary gate, each of said ISDN adapter cards being provided with means (640-670) for handling at least one B-channel, first processing means (140) associated with memory storage (140). The ISDN primary adapter (222) comprising second processing means (100) associated with second memory storage. The method involving the step of: performing a polling (12) in said ISDN primary adapter (222) consisting in the transmission of a specific polling pattern to each of said ISDN adapter cards, in response to the reception of said polling pattern in one of said ISDN adapter cards, transmitting a first pattern consisting of a request pattern (14) to said the processor located in the workstation for requiring a loading of the second memory storage with operational code transferred from the workstation to the ISDN adapter card (210) and the ISDN primary adapter (222), in response to the request pattern received by the main processor (260), transmitting a second pattern to the ISDN adapter (222) via the ISDN adapter card (210) that have transmitted the first pattern, so that the main processor in the workstation and the processor in the ISDN primary adapter recognize the ISDN adapter card that has respectively transmitted the first and third pattern to the workstation and to the ISDN primary adapter (222) be considered as the master ISDN adapter card which will be used in the future for the transmission of the control information and the D-channel. Additionally, that ISDN adapter card is used for the downloading of the operational code from the workstation to the memory storage located into the ISDN primary adapter (222). This results in the possibility of loading the different required software routines in the appropriated locations within the cards so that all work together together to handle a full primary ISDN frame.