公开(公告)号：BR9405158A

公开(公告)日：1995-08-01

申请号：BR9405158

申请日：1994-12-20

Applicant: IBM

Inventor： GALLI CAROL ,  HSU LOUIS L ,  OGURA SEIKI ,  SHEPARD JOSEPH F

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. First, a trench (18) is formed in a silicon substrate (12) having a thin blanket layer (14) of a hard polish-stop material and a photo resist layer (16) (used to pattern the structure) formed thereon. A channel stop region (20) is formed as standard in the trench. Next, the trench is filled with SiO2 using liquid phase oxide deposition above the level of said thin layer. Then the photo resist layer is removed and the SiO2 fill (22) is planarized. Finally, the SiO2 fill is densified and during the thermal cycle, a thin layer (30) of thermal oxide is formed at the fill-substrate interface. The structure can be readily and easily planarized, and voids contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on the resist used to form the trench.

公开(公告)号：DE3784958T2

公开(公告)日：1993-09-30

申请号：DE3784958

申请日：1987-01-23

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L21/225

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：AU6995987A

公开(公告)日：1987-09-24

申请号：AU6995987

申请日：1987-03-12

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：FR2335958A1

公开(公告)日：1977-07-15

申请号：FR7634821

申请日：1976-11-12

Applicant: IBM

Inventor： AOKI TAKAAKI ,  EVRENIDIS PAUL ,  IGARASHI RYO ,  OGURA SEIKI

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/088 ,  H01L29/78 ,  H01L27/06 ,  H01C13/00 ,  H01L29/94

公开(公告)号：DE2653484A1

公开(公告)日：1977-06-30

申请号：DE2653484

申请日：1976-11-25

Applicant: IBM

Inventor： AOKI TAKAAKI ,  EVRENIDIS PAUL ,  IGARASHI RYO ,  OGURA SEIKI

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/088 ,  H01L29/78 ,  H01L27/08