公开(公告)号：JPH0621206A

公开(公告)日：1994-01-28

申请号：JP9569893

申请日：1993-04-22

Applicant: IBM

Inventor： JIYOOJI UIRIAMU DOTSURE ,  OGURA SEIKI ,  NIBUO ROBUEDO

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

Abstract: PURPOSE: To maintain the precision of the thickness of a grinding gage by stopping oxidization, when all the polysilicon has been converted into oxide at the time of forming device layers with certain intervals on an SOI wafer, and making a mesa thin, until it is equal to the height of the upper face of new oxide by chemical machinery type grinding. CONSTITUTION: An oxide layer 20 is provided on a bulk silicon substrate 10, and an epitaxial single-crystal device layer 30 is separated into a pair of mesas 40 by a pair of narrow trenches surrounding the maser and extending to the oxide layer 20, and a trench 32 is provided with an oxide bottom face. A pair of maser-separating trenches 32 are set, so as to be small such that the device intensity on a integrated circuit can be minimized, and a wide region such as a trench 35 can be prevented from tissing-processed. The thickness of the mesa 40 is decreased so as to be controlled precisely, and grinding is continued until the thickness of the mesa can equal the gate thickness of a layer 45, by using a layer equipped with two functions for precisely controlling the thickness for holding the upper face of a wafer to be flat.

公开(公告)号：JPH0855985A

公开(公告)日：1996-02-27

申请号：JP17370995

申请日：1995-07-10

Applicant: IBM

Inventor： RUI RU CHIEN SHIYUU ,  CHIYAN MIN SHIE ,  RINDON RONARUDO ROOGAN ,  JIYATSUKU ARAN MANDERUMAN ,  OGURA SEIKI

IPC: G03F1/08 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide the separate design of field effect transistor(FET) device so as to reduce a leakage current induced along the edge of FET device, especially, submicron FET device to use shallow trench isolation. SOLUTION: An FET device is isolated by shallow trench isolation structure having channel width between 1st and 2nd shallow trenches at the edges of 1st and 2nd shallow trenches. A gate 14 is extended across the channel width between the 1st and the 2nd shallow trenches. The gate has a 1st length at the edge and has a 2nd length shorter than the 1st length between the edges. The 1st length and the 2nd length are related such that a Vt at the edge can be almost equal with a Vt between the edges. The gate structure of the FET device is produced using a unique phase shift mask, and the production of submicron FET device having the extremely short length is enabled.

公开(公告)号：JPS62101034A

公开(公告)日：1987-05-11

申请号：JP19302286

申请日：1986-08-20

Applicant: IBM

Inventor： BEYER KLAUS DIETRICH ,  MAKRIS JAMES STEVE ,  MENDEL ERIC ,  NUMMY KAREN ANN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

公开(公告)号：JPH098159A

公开(公告)日：1997-01-10

申请号：JP13318396

申请日：1996-05-28

Applicant: IBM

Inventor： OGURA SEIKI ,  NIBUO ROBUEDO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit including an EEPROM cell which can be formed in self-alignment manner with high integration density, whose coupling rate is increased, and whose operating margin is improved as a result. SOLUTION: In an integrated circuit which contains an EEPROM cell, the EEPROM cell contains a conduction channel region, a floating gate 50 which is insulated from the conduction channel region and a control gate electrode structure which is insulated from the conduction channel region and the floating gate and which is overlapped with the surface and the side face of the floating gate. The control gate electrode structure contains a control electrode 18 and a conductive sidewall 82 which is ohmic-connected to the control electrode.

公开(公告)号：JPH0846158A

公开(公告)日：1996-02-16

申请号：JP16361395

申请日：1995-06-29

Applicant: IBM

Inventor： RUI RUU CHIEN SHIYUU ,  OGURA SEIKI ,  JIYOOZEFU FURANSHISU SHIEPAADO

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108

Abstract: PURPOSE: To provide a method for forming a trench capacitor type DRAM cell. CONSTITUTION: The DRAM is fabricated by making a trench collar through a single step for extending a shallow trench in the horizontal direction and coating a collar conformally, etching the trench to the final depth and filling the bottom part deeply, doping the side wall lightly and forming a conductive path through a strap 255 formed between the upper surface of a polysilicon inner electrode 240 and an adjacent transistor electrode 124. According to the method, the DRAM can be fabricated by a simplified process where the degree of freedom of processing is enhanced while reducing the cost.

公开(公告)号：JPS62105426A

公开(公告)日：1987-05-15

申请号：JP23024186

申请日：1986-09-30

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SCHULZ RONALD N

IPC: G03F1/00 ,  G03F1/08 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311

公开(公告)号：CA2131668C

公开(公告)日：1999-03-02

申请号：CA2131668

申请日：1994-09-08

Applicant: IBM

Inventor： GALLI CAROL ,  HSU LOUIS L ,  OGURA SEIKI ,  SHEPARD JOSEPH F

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08 ,  H01L21/31

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

公开(公告)号：DE68906095T2

公开(公告)日：1993-10-28

申请号：DE68906095

申请日：1989-06-29

Applicant: IBM

Inventor： AKBAR SHAH ,  KROESEN PATRICIA LAVELLE ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/72 ,  H01L29/52 ,  H01L29/60

Abstract: A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer (12); a base layer (14) disposed over the collector layer; an emitter layer (16) disposed over the base layer; a first sidewall insulating layer (18) disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer (20) disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer (22) formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect (24) disposed on a surface of the base contact extension layer and; a collector contact extension layer (26) formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect (29) disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

公开(公告)号：DE68906095D1

公开(公告)日：1993-05-27

申请号：DE68906095

申请日：1989-06-29

Applicant: IBM

Inventor： AKBAR SHAH ,  KROESEN PATRICIA LAVELLE ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/72 ,  H01L29/52 ,  H01L29/60

Abstract: A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer (12); a base layer (14) disposed over the collector layer; an emitter layer (16) disposed over the base layer; a first sidewall insulating layer (18) disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer (20) disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer (22) formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect (24) disposed on a surface of the base contact extension layer and; a collector contact extension layer (26) formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect (29) disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

公开(公告)号：BR8700839A

公开(公告)日：1987-12-22

申请号：BR8700839

申请日：1987-02-23

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/312 ,  H01L29/94

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.