公开(公告)号：US6278171B2

公开(公告)日：2001-08-21

申请号：US73466800

申请日：2000-12-13

Applicant: IBM

Inventor： ARNDT KENNETH C ,  HSU LOUIS L ,  MANDELMAN JACK A ,  MULLER K PAUL

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

Abstract translation: 用于形成诸如熔丝结构的互连布线结构的方法包括使用相移掩模（具有垂直侧壁倾斜的侧壁和水平表面的开口）在绝缘层中形成开口，在开口中沉积导电材料并除去 来自倾斜侧壁和水平表面的导电材料，其中导电材料作为熔丝链保持在垂直侧壁上。

公开(公告)号：WO2011037710A2

公开(公告)日：2011-03-31

申请号：PCT/US2010046267

申请日：2010-08-23

Applicant: IBM ,  HSU LOUIS L ,  OUYANG XU ,  YANG CHIH-CHAO

Inventor： HSU LOUIS L ,  OUYANG XU ,  YANG CHIH-CHAO

IPC: G11C11/24 ,  G11C11/34

CPC classification number: H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract translation: 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电连接电容器的开关装置。 开关装置包括感测单元，该感测单元被配置为检测电容器的泄漏水平，使得如果泄漏电流超过预定水平，则开关装置电切断电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或两个以上的电容器板。 采用泄漏传感器和开关装置来电切断电容器阵列中任何变得泄漏的电容器模块，由此保护电容器阵列免于过度的漏电。

公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO0229825A3

公开(公告)日：2002-08-01

申请号：PCT/US0127001

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEHMANN GUNTHER ,  FRANKOWSKY GERD ,  HSU LOUIS L ,  REITH ARMIN

IPC: G01R31/3183 ,  G01R31/319 ,  G11C29/10 ,  G11C29/56 ,  G11C29/00

CPC classification number: G01R31/318378 ,  G01R31/3183 ,  G01R31/31926 ,  G11C29/10 ,  G11C29/56

Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required.

公开(公告)号：JP2003031781A

公开(公告)日：2003-01-31

申请号：JP2002132064

申请日：2002-05-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： HSU LOUIS L ,  SHI LEATHEN ,  WANG LI-KONG

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/76256

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a microwave circuit and a radio frequency circuit in a silicon on a sapphire substrate.
SOLUTION: An improved method for fabricating a silicon on sapphire structure and/or device is disclosed. In one suitable embodiment, a single silicon oxide layer is interposed between a silicon layer and a sapphire layer by attaching the silicon oxide layer onto the silicon layer through growth or deposition and then attaching the sapphire layer to the oxide layer through wafer bonding. In another embodiment, a first silicon oxide layer is attached to the silicon layer through growth or deposition. Subsequently, a second silicon oxide layer is attached to the sapphire layer by deposition, for example. Thereafter, the first silicon oxide layer and the second silicon oxide layer are bonded by wafer bonding technology.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种在蓝宝石衬底上的硅中制造微波电路和射频电路的方法。 解决方案：公开了一种用于制造蓝宝石结构和/或器件上的硅的改进方法。 在一个合适的实施例中，通过生长或沉积将硅氧化物层附着在硅层上，然后通过晶片接合将蓝宝石层附着到氧化物层，将硅单层氧化硅层介于硅层和蓝宝石层之间。 在另一个实施例中，通过生长或沉积将第一氧化硅层附着到硅层。 随后，例如通过沉积将第二氧化硅层附着到蓝宝石层。 此后，通过晶片接合技术将第一氧化硅层和第二氧化硅层接合。

公开(公告)号：JP2003023155A

公开(公告)日：2003-01-24

申请号：JP2002127052

申请日：2002-04-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L ,  RADENS CARL J ,  SHEPARD JOSEPH F JR

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET(metal oxide semiconductor field effect transistor) and a method for manufacturing the MOSFET capable of eliminating the overlap of a gate dielectric and a source/drain region with high reliability.
SOLUTION: This method for manufacturing a MOSFET comprises the process of patterning a gate laminate constituted of a gate dielectric 20 arid a gate conductor 30 formed on a substrate 10, and the process of modifying the gate dielectric 20 beneath the gate dielectric 30 so that the gate dielectric 20 can have a central portion and a modified dielectric region 70 adjacent to the central portion. The modified dielectric region 70 has a lower dielectric constant than that of the gate dielectric 20, and the central portion is shorter than the gate conductor 30.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种MOSFET（金属氧化物半导体场效应晶体管）以及能够以高可靠性消除栅极电介质和源极/漏极区域的重叠的MOSFET的制造方法。 解决方案：用于制造MOSFET的方法包括对由栅极电介质20和形成在衬底10上的栅极导体30构成的栅极叠层的图案化以及在栅极电介质30下面改变栅极电介质20的工艺， 栅极电介质20可以具有与中心部分相邻的中心部分和改进的电介质区域70。 改性电介质区域70具有比栅极电介质20低的介电常数，并且中心部分比栅极导体30短。

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：WO0193271A2

公开(公告)日：2001-12-06

申请号：PCT/US0117267

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU LOUIS L ,  WEINFURTNER OLIVER ,  JI BRIAN L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

CPC classification number: G11C8/08 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4078 ,  G11C2207/104

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

Abstract translation: 通过使用以一小部分监视晶体管阈值电压跟踪的偏置电压调节来获得改进的晶体管阵列器件性能。 电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。 这些优点是特别是当通过至少一个监视晶体管的实际阈值电压的一部分进行跟踪来调节通常提供给阵列的至少两个偏置电压时。 性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗以及（在存储器单元的情况下）改进的保留时间。

公开(公告)号：DE112010002919B4

公开(公告)日：2015-01-22

申请号：DE112010002919

申请日：2010-08-23

Applicant: IBM

Inventor： OUYANG XU ,  YANG CHIH-CHAO ,  HSU LOUIS L

IPC: G11C11/24 ,  G11C11/34 ,  H01L21/822 ,  H01L27/06 ,  H02H7/16

Abstract: Halbleiterstruktur, welche eine Matrix von Kondensatormodulen (100) umfasst, wobei jedes der Kondensatormodule das Folgende umfasst: einen Kondensator (C), welcher eine erste Elektrode (110), eine zweite Elektrode (120) und ein dielektrisches Material umfasst, das zwischen der ersten Elektrode und der zweiten Elektrode angeordnet ist; und eine Schalteinheit (140), welche dafür konfiguriert ist, den Kondensator von einem Spannungsversorgungsknoten (Vdd) elektrisch zu trennen, wobei die Schalteinheit einen Feldeffekttransistor (P2) und eine Sensoreinheit (142) umfasst, welche dafür konfiguriert ist, einen Leckstrom durch den Kondensator hindurch zu erkennen und wobei die Sensoreinheit einen ersten Feldeffekttransistor des p-Typs (P1) umfasst, es sich bei dem Feldeffekttransistor um einen zweiten Feldeffekttransistor des p-Typs handelt und der erste und zweite Feldeffekttransistor des p-Typs in einer Parallelschaltung zwischen den Spannungsversorgungsknoten und einen Knoten (Knoten B) des Kondensators geschaltet sind.

公开(公告)号：DE112010002919T5

公开(公告)日：2012-05-24

申请号：DE112010002919

申请日：2010-08-23

Applicant: IBM

Inventor： OUYANG XU ,  YANG CHIH-CHAO ,  HSU LOUIS L

IPC: G11C11/24 ,  G11C11/34

Abstract: Eine modulare Kondensatormatrix umfasst mehrere Kondensatormodule. Jedes Kondensatormodul umfasst einen Kondensator und eine Schalteinheit, welche dafür konfiguriert ist, den Kondensator elektrisch abzutrennen. Die Schalteinheit umfasst eine Sensoreinheit, welche dafür konfiguriert ist, die Stärke des Leckstroms des Kondensators zu erkennen, so dass die Schalteinheit den Kondensator elektrisch abtrennt, wenn der Leckstrom eine vorgegebene Stärke übersteigt. Jedes Kondensatormodul kann eine einzelne Kondensatorplatte, zwei Kondensatorplatten oder mehr als zwei Kondensatorplatten umfassen. Die Leckstromsensoren und Schalteinheiten werden verwendet, um jedes Kondensatormodul aus der Kondensatormatrix elektrisch abzutrennen, das zu lecken beginnt, wodurch die Kondensatormatrix vor einem übermäßigen elektrischen Leckstrom geschützt wird.