公开(公告)号：JP2004229163A

公开(公告)日：2004-08-12

申请号：JP2003016979

申请日：2003-01-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MORI MASAYA ,  WATANABE SHINPEI ,  SUNANAGA TOSHIO ,  TAKATSU YOSHIHISA

IPC: G06F7/02 ,  G06F17/30 ,  H04L12/46

CPC classification number: G06F17/30949 ,  G06F7/02 ,  Y10S707/99933

Abstract: PROBLEM TO BE SOLVED: To retrieve fixed length data such as MAC addresses to be stored in a data table in large bulk at high speed. SOLUTION: This fixed data retrieval device is provided with a hash operation means 11 for calculating and outputting a hash value of inputted fixed length data, a data table memory 14 consisting of N (N is an integer ≥2) memory banks and for storing the data table in which many pieces of fixed length data are held, a pointer table memory 13 for storing a memory pointer table in which memory addresses of storing destinations of each piece of fixed length data are held by using the hash value as an index and a comparison means 15 for simultaneously comparing a plurality of pieces of fixed length data stored in the same memory address of the N memory banks with one piece of fixed length data inputted in the hash operation means and for outputting a comparison result. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JPH10111828A

公开(公告)日：1998-04-28

申请号：JP25712796

申请日：1996-09-27

Applicant: IBM

Inventor： WATANABE SHINPEI ,  SUNANAGA TOSHIO

IPC: G06F12/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096

Abstract: PROBLEM TO BE SOLVED: To provide a memory system which is constituted of DRAM capable of executing seamless operation by not only a reading operation but also a writing operation by preventing band width from being substantially reduced as compared with a clock pulse frequency regardless of in which bank access is performed and in which order it is executed. SOLUTION: Memory array is separated from data in an early stage by applying pre-fetch mechanism in reading and writing so as to prevent the energizing and pre-fetching operations, etc., which are the ones required for succeeding reading in memory array from being the main cause of reduction in access speed. Two-fold data of an array time constant is pre-fetched so that the both of reading ans writing are simultaneously realized concerning the seamless operation by singlel bank configuration in spite of any kind of low-access.

公开(公告)号：HK34993A

公开(公告)日：1993-04-16

申请号：HK34993

申请日：1993-04-08

Applicant: IBM

Inventor： AOKI YUTAKA ,  WATANABE SHINPEI

IPC: G09G5/00 ,  G06F3/147 ,  G06F3/153 ,  G06T11/00 ,  G09G5/02 ,  G09G5/39 ,  G09G1/28 ,  G09G1/16

Abstract: A color image display apparatus includes an image memory comprising a plurality of memory planes, each corresponding to a specific color. The memory planes are simultaneously addressed by a common address from a CPU so as to either write image data on data busses respectively connected thereto or read image data out to these data busses. The apparatus also includes a read/write circuit comprising means for distributing the image data to be written in the image memory to the data bus of each memory plane, first selecting means for selecting one or more memory planes in which the image data are to be written, a plurality of read registers corresponding to the respective memory planes, and second selecting means for selecting one or more read registers whose contents are to be outputted to the CPU. In this apparatus, the write operation is performed in only a selected memory plane or planes while the read operation is performed in all of the memory planes simultaneously.

公开(公告)号：CA1233279A

公开(公告)日：1988-02-23

申请号：CA478047

申请日：1985-04-01

Applicant: IBM

Inventor： AOKI YUTAKA ,  WATANABE SHINPEI

IPC: G09G5/00 ,  G06F3/147 ,  G06F3/153 ,  G06T11/00 ,  G09G5/02 ,  G09G5/39 ,  G09G1/00

Abstract: COLOR IMAGE DISPLAY APPARATUS In a color image display apparatus, a plurality of color corresponding memory planes forming an image memory, are simultaneously addressed by a common address from a CPU so as to either write image data on data busses respectively connected thereto, or read image data out on these data busses. The image data to be written in the image memory are distributed to the data bus of each memory plane in the R/W circuit. These image data are written in a memory plane or planes that are selected by first selecting means. Reading is simultaneously performed in each memory plane, and the read image data are loaded in read registers that are provided for the respective memory planes. The contents of a read register or registers among them that are selected by second selecting means are outputted to the CPU.