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    SEMICONDUCTOR MEMORY
    33.
    发明专利
    SEMICONDUCTOR MEMORY 未知

    公开(公告)号：CA1211212A

    公开(公告)日：1986-09-09

    申请号：CA452131

    申请日：1984-04-16

    Applicant: IBM

    Inventor： WIEDMANN SIEGFRIED K

    IPC: G11C11/41 ,  G11C5/02 ,  G11C8/14 ,  G11C8/00

    Abstract: SEMICONDUCTOR MEMORY A semiconductor memory is described whose word lines are divided into several partial word lines or partitions, wherein each partial word line is connected to a word switch and all word switches of a word line are selected and controlled via a first word control line and a second word control line.

    35.
    发明专利
    未知

    公开(公告)号：FR2371063A1

    公开(公告)日：1978-06-09

    申请号：FR7729891

    申请日：1977-09-29

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L27/08

    Abstract: Improved integrated bipolar semiconductor structures and a method of fabricating same are disclosed. The logic circuit structures disclosed have enhanced density and speed power product. The teaching of the disclosed logic circuit structures includes utilization and extension of the known concepts of Current Hogging Injection Logic (CHIL) and Integrated Injection Logic (I2L). The disclosed method of fabrication includes a minimum number of process steps, where each step is well within the state of the art and does not contain critical alignment problems.

    BIPOLAR CAPACITIVE MEMORY CELL
    38.
    发明专利
    BIPOLAR CAPACITIVE MEMORY CELL 未知

    公开(公告)号：CA948328A

    公开(公告)日：1974-05-28

    申请号：CA127429

    申请日：1971-11-12

    Applicant: IBM

    Inventor： WIEDMANN SIEGFRIED K

    IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/07 ,  H01L27/102

    Abstract: This specification discloses a stored charge storage cell for monolithic memories. The cell comprises a device akin to a silicon-controlled rectifier and can be schematically illustrated as an NPN and a PNP transistor connected together in what is commonly called a hook circuit. A fixed potential is applied to the semiconductor zone of the device not commonly used as a terminal for a silicon-controlled rectifier so that the cell is prevented from latching as a silicon-controlled rectifier or hook circuit would normally latch. The charge on the capacitance of collector-base PN junctions of the NPN and PNP transistors is then controlled to store data in the cell.

    IMPROVEMENTS IN SEMICONDUCTOR DEVICES
    39.
    发明专利
    IMPROVEMENTS IN SEMICONDUCTOR DEVICES 未知

    公开(公告)号：GB1298059A

    公开(公告)日：1972-11-29

    申请号：GB3409671

    申请日：1971-07-21

    Applicant: IBM

    Inventor： WIEDMANN SIEGFRIED K

    IPC: H01L21/761 ,  H01L27/00 ,  H01L27/07

    Abstract: 1298059 Semi-conductor devices INTERNA. TIONAL BUSINESS MACHINES CORP 21 July 1971 [5 Aug 1970] 34096/71 Heading H1K An isolated low-beta transistor is produced by forming a highly doped base region simultaneously with a similarly doped isolation wall which surrounds the transistor. The resulting structure may be utilized as a self-isolated diode in the same isolated region as other such diodes or high-beta transistors. As shown, Fig. 1, a buried N + type subcollector region 2 is formed between a P- type Si substrate 1 and an N type epitaxial layer 3. Conventional masking steps are utilized for the diffusion of a P + type isolation wall 4 and simultaneously two P + type base regions 5, 6 are diffused-in above the subcollector region 2 which prevents them contacting the substrate. A common P type base region 9 is then diffusedin surrounding both P + type regions 5, 6 into which are subsequently diffused N + type emitter regions 10, 11. The resulting structure is similar to a conventional double-emitter transistor but the additional P + type base regions 5, 6 reduce the beta to such an extent that the emitter-base junctions may be utilized as diodes 7 1 , 8 1 as illustrated in Fig. 1A, the base region providing the common anode connection. In a modification, Fig. 2 (not shown), a P+ type base region is formed round only one of the emitter regions so that the other emitter forms part of a high beta transistor the base of which is connected to a diode provided by the emitter-base junction of the low beta transistor. The device should be operated so that the basecollector junction of the low beta transistor is always reverse biased and this may be achieved by arranging that the high beta transistor operates in a non-saturating mode. In another modification, Fig. 3 (not shown), two separate P type base regions are provided surrounding the two P + type base regions. This structure provides two mutually isolated diodes. In some of the structures the P type base region performs no significant electrical function and may be omitted. It is, however, preferable to perform this base diffusion since the formation of a thin oxide layer in place of the thick oxide resulting from the isolation diffusion during the conventional processing facilitates the opening of the emitter diffusion windows.

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