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    Monolithic semiconductor memory
    1.
    发明授权
    Monolithic semiconductor memory 失效
    单片半导体存储器

    公开(公告)号：US3643235A

    公开(公告)日：1972-02-15

    申请号：US3643235D

    申请日：1969-12-05

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIGFRIED K

    IPC: G11C11/411 ,  G11C15/00 ,  H01L21/00 ,  H01L27/00 ,  H01L27/07 ,  H01L27/082 ,  H01L27/10 ,  H01L27/102 ,  H03K3/286 ,  H03K3/288 ,  H03K3/35 ,  G11C11/40 ,  H03K3/281

    CPC classification number: H03K3/35 ,  G11C11/4113 ,  G11C11/4116 ,  G11C15/00 ,  H01L21/00 ,  H01L27/00 ,  H01L27/0744 ,  H01L27/0821 ,  H01L27/0828 ,  H01L27/10 ,  H01L27/1022 ,  H01L27/1025 ,  H03K3/286 ,  H03K3/288

    Abstract: This specification discloses a storage cell which employs inversely operated and transverse transistors to reduce storage cell size accessing times and power consumption when the cell is fabricated in monolithic form. Two cross-connected transistors are inversely operated so that they share a common emitter region with a separate base region and collector region for each of the cross-connected transistors. In this way, the transistors can be fabricated in a single diffusion region. The collector of each of the cross-connected transistors is connected to the collector of a load transistor of the opposite type transistor and to the base of an addressing transistor having its emitter connected to the sense line and its collector connected to the base of the load transistors. The two addressing and load transistors are formed in a single isolation zone with collector and base regions of the addressing transistors serving also as the base and collector regions respectively of the load transistors which are fabricated as transverse transistors with a common emitter region.

    Abstract translation: 本说明书公开了一种存储单元，其使用反向操作和横向晶体管来减小当单元以单体形式制造存储单元尺寸时的存取时间和功耗。 两个交叉连接的晶体管被​​反向工作，使得它们共享具有用于每个交叉连接的晶体管的单独的基极区域和集电极区域的公共发射极区域。 以这种方式，可以在单个扩散区域中制造晶体管。 每个交叉连接的晶体管的集电极连接到相对型晶体管的负载晶体管的集电极，并连接到寻址晶体管的基极，其发射极连接到感测线，其集电极连接到负载的基极 晶体管。 两个寻址和负载晶体管形成在单个隔离区域中，寻址晶体管的集电极和基极区域也分别用作负载晶体管的基极和集电极区域，这些区域被制造为具有公共发射极区域的横向晶体管。

    Monolithically integrable digital basic circuit
    2.
    发明授权
    Monolithically integrable digital basic circuit 失效
    单片可积分数字基本电路

    公开(公告)号：US3922565A

    公开(公告)日：1975-11-25

    申请号：US41958173

    申请日：1973-11-28

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

    IPC: H01L27/00 ,  H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H03K19/013 ,  H01L27/04 ,  H03K19/12 ,  H03K19/34

    CPC classification number: H03K19/013 ,  H01L27/00 ,  H01L27/0214 ,  H01L27/0237 ,  H01L27/0688 ,  H01L27/0766 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/087 ,  Y10S148/096 ,  Y10S148/117

    Abstract: Disclosed is a circuit showing a switching transistor whose base is connected to diodes forming the logical inputs and whose collector forms the logical output. Power supply is effected by charge carrier injection into the emitter of the switching transistor. To this end, a complementary transistor is employed, whose emitter terminal is connected to a voltage source and whose collector and base are linked with the base and the emitter of the switching transistor respectively. The collector of the switching transistor and the diodes are made up of Schottky contacts on the semiconductor zone forming the base of the switching transistor. Also disclosed is a semiconductor structure of the circuit consisting of a layered structure with a first, second, and third semiconductor layers of alternating conductivity types. The first and second layers are ohmically contacted, whereas the third layer is provided with the Schottky contacts. The second layer simultaneously forms the emitter of the switching transistor and the base of the complementary transistor whose emitter is made up of the first layer. The third layer simultaneously forms the collector of the complementary transistor and the base of the switching transistor.

    Abstract translation: 公开了一种开关晶体管的电路，其基极连接到形成逻辑输入的二极管，其集电极形成逻辑输出。 电源通过电荷载流子注入开关晶体管的发射极来实现。 为此，采用互补晶体管，其发射极端子连接到电压源，其集电极和基极分别与开关晶体管的基极和发射极连接。 开关晶体管和二极管的集电极由形成开关晶体管基极的半导体区上的肖特基触点构成。 还公开了由具有交替导电类型的第一，第二和第三半导体层的分层结构组成的电路的半导体结构。 第一层和第二层被欧姆接触，而第三层设置有肖特基接触。 第二层同时形成开关晶体管的发射极和互补晶体管的基极，其发射极由第一层组成。 第三层同时形成互补晶体管的集电极和开关晶体管的基极。

    6.
    发明专利
    未知

    公开(公告)号：DD137771A5

    公开(公告)日：1979-09-19

    申请号：DD20607877

    申请日：1977-11-14

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L27/08

    Abstract: Improved integrated bipolar semiconductor structures and a method of fabricating same are disclosed. The logic circuit structures disclosed have enhanced density and speed power product. The teaching of the disclosed logic circuit structures includes utilization and extension of the known concepts of Current Hogging Injection Logic (CHIL) and Integrated Injection Logic (I2L). The disclosed method of fabrication includes a minimum number of process steps, where each step is well within the state of the art and does not contain critical alignment problems.

    8.
    发明专利
    未知

    公开(公告)号：FR2371063A1

    公开(公告)日：1978-06-09

    申请号：FR7729891

    申请日：1977-09-29

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L27/08

    Abstract: Improved integrated bipolar semiconductor structures and a method of fabricating same are disclosed. The logic circuit structures disclosed have enhanced density and speed power product. The teaching of the disclosed logic circuit structures includes utilization and extension of the known concepts of Current Hogging Injection Logic (CHIL) and Integrated Injection Logic (I2L). The disclosed method of fabrication includes a minimum number of process steps, where each step is well within the state of the art and does not contain critical alignment problems.

    BI-POLAR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FABRICATING SAME
    10.
    发明专利
    BI-POLAR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FABRICATING SAME 未知

    公开(公告)号：CA1092722A

    公开(公告)日：1980-12-30

    申请号：CA287816

    申请日：1977-09-29

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L27/04 ,  H03K19/08

    Abstract: An integrated logic circuit is formed on a layer of semi-con-ductive material of one conductive type. The first region of the opposite conductivity type is formed in the layer with no contact means formed on or in it so that no external electrical signals can be applied to the first region. A second region of the one conductivity type is formed within the first region and provides, with the first region and the layer, a vertical transistor structure. Third and fourth regions of the opposite conductivity type are formed in the layer at positions spaced away from each other and from the first region so that the layer forms the base region of both a first lateral transistor comprising the fourth and third regions, and of a second lateral transistor comprising the third and first regions. Means operable to inject current into the layer performed in the base region of both lateral transistors through the fourth region. An input circuit for applying input voltage signals to the third region to control the current distribution between the two lateral transistors and thus the current supplied to the first region is formed in the base region of the vertical transistor. An output circuit comprises the controlled current path of the vertical transistor. the vertical transistor is normally operated so that the second region acts as the collector zone. One or more further regions of the opposite conductivity type may be formed in the layer at positions spaced away from each other and from the first, third and fourth regions. Each further region has an individual further input circuit whereby a pattern of input voltage signals applied simultaneously to the third and further regions determines the base currents applying to the base of the vertical transistor.

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