公开(公告)号：US11316066B2

公开(公告)日：2022-04-26

申请号：US16708014

申请日：2019-12-09

Applicant: IMEC VZW

Inventor： Soeren Steudel ,  Alexander Mityashin ,  Eric Beyne ,  Maarten Rosmeulen

IPC: H01L33/00 ,  H01L25/075 ,  H01L27/146 ,  H01L33/06 ,  H01L33/62

Abstract: An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (μLED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

公开(公告)号：US20210159207A1

公开(公告)日：2021-05-27

申请号：US17102249

申请日：2020-11-23

Applicant: IMEC vzw

Inventor： Jaber Derakhshandeh ,  Eric Beyne ,  Gerald Peter Beyer

IPC: H01L23/00 ,  B23K1/008

Abstract: A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

公开(公告)号：US20200185566A1

公开(公告)日：2020-06-11

申请号：US16708014

申请日：2019-12-09

Applicant: IMEC VZW

Inventor： Soeren Steudel ,  Alexander Mityashin ,  Eric Beyne ,  Maarten Rosmeulen

IPC: H01L33/00 ,  H01L25/075 ,  H01L33/06 ,  H01L33/62 ,  H01L27/146

Abstract: An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (μLED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

公开(公告)号：US10334755B2

公开(公告)日：2019-06-25

申请号：US15388914

申请日：2016-12-22

Applicant: IMEC VZW

Inventor： Herman Oprins ,  Vladimir Cherman ,  Eric Beyne

IPC: H05K7/20 ,  H05K5/06 ,  H01L23/473

Abstract: A liquid cooling system for cooling an electronic device comprising a chip or a chip package comprising a chip is described. The liquid cooling system comprises an inlet plenum comprising a coolant feeding channel oriented substantially parallel with the plane of a main surface to be cooled of the chip and a plurality of inlet cooling channels fluidically connected to the coolant feeding channel and arranged vertically for impinging a liquid coolant directly on said main surface of the chip. The vertically oriented inlet cooling channels are substantially parallel to vertically oriented outlet cooling channels and are separated by a thermally isolating material. The liquid cooling system further comprises at least one cavity wherein a plurality of inlet and outlet cooling channels end. The cavity is arranged for allowing interaction between the liquid coolant and the main surface of the chip and thus comprises a heat transfer region.

公开(公告)号：US20180068984A1

公开(公告)日：2018-03-08

申请号：US15697285

申请日：2017-09-06

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Joeri De Vos ,  Stefaan Van Huylenbroeck

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/3065 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80125 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/14

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.

公开(公告)号：US20170301646A1

公开(公告)日：2017-10-19

申请号：US15604454

申请日：2017-05-24

Applicant: IMEC VZW

Inventor： Soon-Wook Kim ,  Lan Peng ,  Patrick Verdonck ,  Robert Miller ,  Gerald Peter Beyer ,  Eric Beyne

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L21/02065 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31053 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03845 ,  H01L2224/03848 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/32501 ,  H01L2224/80048 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/83031 ,  H01L2224/83047 ,  H01L2224/83048 ,  H01L2224/83359 ,  H01L2924/00012 ,  H01L2924/0504 ,  H01L2924/00014 ,  H01L2924/20106 ,  H01L2924/2011

Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

公开(公告)号：US20170196120A1

公开(公告)日：2017-07-06

申请号：US15388914

申请日：2016-12-22

Applicant: IMEC VZW

Inventor： Herman Oprins ,  Vladimir Cherman ,  Eric Beyne

IPC: H05K7/20 ,  H05K5/06

CPC classification number: H05K7/20272 ,  H01L23/4735 ,  H01L24/00 ,  H05K5/06

Abstract: A liquid cooling system for cooling an electronic device comprising a chip or a chip package comprising a chip is described. The liquid cooling system comprises an inlet plenum comprising a coolant feeding channel oriented substantially parallel with the plane of a main surface to be cooled of the chip and a plurality of inlet cooling channels fluidically connected to the coolant feeding channel and arranged vertically for impinging a liquid coolant directly on said main surface of the chip. The vertically oriented inlet cooling channels are substantially parallel to vertically oriented outlet cooling channels and are separated by a thermally isolating material. The liquid cooling system further comprises at least one cavity wherein a plurality of inlet and outlet cooling channels end. The cavity is arranged for allowing interaction between the liquid coolant and the main surface of the chip and thus comprises a heat transfer region.

公开(公告)号：US20170186733A1

公开(公告)日：2017-06-29

申请号：US15457744

申请日：2017-03-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Vikas Dubey ,  Ingrid De Wolf ,  Eric Beyne

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/02185 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/80121 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80203 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81894 ,  H01L2224/81907 ,  H01L2224/83143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

公开(公告)号：US20240213120A1

公开(公告)日：2024-06-27

申请号：US18393221

申请日：2023-12-21

Applicant: IMEC vzw

Inventor： Herman Oprins ,  Geert Van der Plas ,  Eric Beyne ,  Pieter Woeltgens

IPC: H01L23/48 ,  H01L23/46 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/46 ,  H01L23/5283 ,  H01L25/0657

Abstract: A micro-electronic component, for example an integrated circuit chip, is provided. In one aspect, the component includes a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion at its front side. A back side power delivery network (PDN) is present at the back side of the component, with via connections connecting the PDN to the FEOL and BEOL portions. The back side PDN includes a “dry part” and a “wet part,” where the dry part includes multiple interconnect levels of the PDN embedded in a dielectric material. The “wet part” includes the remaining PDN levels which are not embedded in a dielectric but which are part of a manifold structure configured to receive therein a flow of cooling fluid in order to remove heat generated by the devices in the FEOL portion.

公开(公告)号：US20240121914A1

公开(公告)日：2024-04-11

申请号：US18480029

申请日：2023-10-03

Applicant: IMEC VZW

Inventor： Vladimir Cherman ,  Herman Oprins ,  Eric Beyne

IPC: H05K7/20

CPC classification number: H05K7/20327 ,  H05K7/20318

Abstract: A cooling device configured to be mounted in close proximity to an electronic component that is to be cooled is provided. In one aspect, the device includes impingement channels and return channels for guiding a flow of cooling fluid towards and away from a cooled surface of the electronic component. The device also includes a heat exchanger and a pump, so that the flow cycle of a cooling fluid is fully confined within the device itself. The impingement channels, the return channels, and the heat exchanger are integrated in a common housing, which includes an inlet opening and an outlet opening for coupling the device to a refrigerant loop. The pump may be a micropump mounted directly on the housing and coupled to the inlet and outlet openings in the housing. A cooling system including the device and the refrigerant loop is also provided.