公开(公告)号：DE10148521A1

公开(公告)日：2003-04-24

申请号：DE10148521

申请日：2001-10-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/00

Abstract: An integrated memory has a selection circuit for setting a selectable latency-relative to a clock signal between a beginning of a read access and the provision of the data to outside the memory. A detection circuit compares data to be output with desired data and serves for setting the latency depending on the comparison result. The selection circuit receives a control signal, by means of which the latency can be set. In the event of noncorrespondence between the data read out and the desired data, the latency is increased by the detection circuit. This enables an accurate and error-free on-chip setting of a so-called CAS latency for a read-out operation of the memory.

公开(公告)号：DE10110273A1

公开(公告)日：2002-09-19

申请号：DE10110273

申请日：2001-03-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTENSCHLAGER RAINER ,  BROX MARTIN ,  KEYSERLINGK ALBERT GRAF VON

IPC: G05F1/46 ,  G05F1/10

Abstract: A voltage generator for producing an internal supply voltage has a standby voltage generator and a voltage generator for normal operation that are controlled in common by a reference voltage. In addition, a comparator stage is provided whose switching threshold is set lower than the reference voltage by using a voltage divider that is connected to the reference voltage. The additional comparator stage thus activates the voltage generator for normal operation when the internally produced voltage falls below its switching threshold so that the internal supply voltage is stabilized.

公开(公告)号：DE10005620A1

公开(公告)日：2001-08-30

申请号：DE10005620

申请日：2000-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: H03K19/003 ,  H03K5/13 ,  H03K19/0175 ,  G11C7/00

Abstract: In order to provide a more flexible adjustment of signal delay times in a circuit configuration containing a line device and a number of electronic components accessing it, it is proposed to add additional capacitances, which can be varied in a controllable manner. In addition, the capacitances are to formed in a region of the existing components.

公开(公告)号：DE19944738C2

公开(公告)日：2001-08-02

申请号：DE19944738

申请日：1999-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  PFEFFERL KARL-PETER

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C8/00

Abstract: The segmented word line architecture has two master word lines, to which sub-word lines are alternately allocated. Two memory banks can thus be alternately assigned to the sub-word lines.

公开(公告)号：DE502004008797D1

公开(公告)日：2009-02-12

申请号：DE502004008797

申请日：2004-11-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G05F1/46

Abstract: One aspect of the invention relates to a voltage regulation process as well as to a voltage regulation system. A first voltage, present at an input of the voltage regulating system, is changed into a second voltage, which can be tapped at an output of the voltage regulation system, with a first device for generating an essentially constant voltage from the first voltage, or a voltage derived from it. A further device is provided for generating a further voltage from the first voltage or a voltage derived from it, in particular a voltage which can be higher than the voltage generated by the first device.

公开(公告)号：DE102006024016A1

公开(公告)日：2007-11-29

申请号：DE102006024016

申请日：2006-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPIRKL WOLFGANG ,  BROX MARTIN

IPC: G11C29/12

Abstract: The memory (1) has an input/output circuit (3) connected with memory cells (2) of a memory field (4) and exchanges data with the memory cells. An output register (5) is connected with the input/output circuit. An input register (6) is connected with a data input (13) and with the input/output circuit. The data are provided into the memory cells over the data input and the input register. The output register continues to give test data to the input register in the test mode, and the test data are transmitted from the input register for the input/output circuit. An independent claim is also included for a method for testing a random access memory.

公开(公告)号：DE102004054546A1

公开(公告)日：2006-05-24

申请号：DE102004054546

申请日：2004-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  KUZMENKA MAKSIM

IPC: H03K19/003

公开(公告)号：DE10333280A1

公开(公告)日：2005-03-03

申请号：DE10333280

申请日：2003-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C11/4096 ,  G06F12/00

Abstract: The invention relates to a semi-conductor memory component and process for operating a semi-conductor memory component, including activating the memory cells of a memory cell array, when one or several memory cell(s) included in the first set of memory cells need(s) to be accessed, accessing the corresponding memory cell or memory cells, deactivating the memory cells contained in a first set of memory cells, when one or several further memory cells that are not included in the first set of memory cells need(s) to be accessed, and prematurely deactivating the memory cells included in the first set of memory cells, when a predetermined time period or number of pulses after one or several memory cells included in the first set of memory cells have last been accessed first no further accessing of one or several of the memory cells included in the first set of memory cells takes place.

公开(公告)号：DE10214304B4

公开(公告)日：2004-10-21

申请号：DE10214304

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

IPC: G06F1/06 ,  H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  H03L7/07 ,  H03L7/081 ,  G06F1/12

Abstract: Device for production of two signals (11,12) with a predetermined distance between corresponding signal flanks. Said device comprises: a first controllable time delay device (5A) for generation of a delayed internal clock signal from a first clock signal (3); a second controllable time delay device (5B) for generation of a displaced inverted clock signal from a complementary clock signal (4); and first and second control signal generators (6-8; 9-10). The invention also relates to a corresponding method.

公开(公告)号：DE10230168B4

公开(公告)日：2004-05-27

申请号：DE10230168

申请日：2002-07-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

IPC: G05F5/08 ,  G11C7/10 ,  H03G3/00 ,  H03K3/356 ,  H03K5/01 ,  H03L5/00

Abstract: The invention involves a voltage converter device ( 101 a , 101 b) for converting a signal (in) at an initial voltage level (vint) into a signal (DatoV) at a second voltage level (vint) differing from the first, in which voltage converter device ( 101 a , 101 b) has an amplifier device ( 102 ), and where the amplifier device ( 102 ) uses a second amplifier device output signal (bout) to generate signals (DatoV) at the second voltage level (vddq).