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    SELECT-FREE ACCESS TYPE SEMICONDUCTOR MEMORY COMPRISING BUS SYSTEM ORIENTED IN TWO PLANES
    2.
    发明专利
    SELECT-FREE ACCESS TYPE SEMICONDUCTOR MEMORY COMPRISING BUS SYSTEM ORIENTED IN TWO PLANES 失效

    公开(公告)号：JP2000339990A

    公开(公告)日：2000-12-08

    申请号：JP2000115370

    申请日：2000-04-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  PFEFFERL KARL-PETER

    IPC: G06F12/16 ,  G06F11/20 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To allow a plurality of redundant data lines to be flexibly associated with different groups by allowing a bus line on a first plane to be connected to all of input/output lines and all of data lines and allowing a plurality of independent partial buses on a second plane to be connected to data lines in at least two groups and an input/output line of each one group. SOLUTION: Data lines MDQii, of groups U1 to U8 are respectively connectable to IO lines RWDii of groups IO1 to IO4 via bus systems on two planes. All of bus lines Ai on a first plane A are connectable to all of data lines MDQ11, to MDQ88, redundant lines MDQ1R to MDQ8R, and IO lines RWD11 to RWD48. Bus lines Bi1 to Bi8 on a second plane composed of partial buses B1 to B4 are respectively connectable to two groups of the data lines MDQi1 to MDQi8, the redundant line MDQR, and one group of the IO lines RWDi1 to RWDi8.

    SEMICONDUCTOR MEMORY WITH MEMORY BANK
    3.
    发明专利
    SEMICONDUCTOR MEMORY WITH MEMORY BANK 失效

    公开(公告)号：JP2000315387A

    公开(公告)日：2000-11-14

    申请号：JP2000113867

    申请日：2000-04-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LE THOAI-THAI ,  TRUNK ANDREA ,  PFEFFERL KARL-PETER

    IPC: G11C8/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/408

    Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor memory having memory banks in which a design cost for a memory bank decoder is small. SOLUTION: In a semiconductor memory having memory banks, plural memory banks are operated by a memory bank decoder. Even if two groups of the memory bank are controlled through the same memory bank decoder, switching between the memory bank decoders is performed by using a pre- decoder. Thereby, layout of the memory bank decoder having comparatively small memory capacity can be succeeded to memories of memory bank decoder having comparatively large capacity.

    5.
    发明专利
    未知

    公开(公告)号：DE50006865D1

    公开(公告)日：2004-07-29

    申请号：DE50006865

    申请日：2000-04-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX DR ,  PFEFFERL KARL-PETER

    IPC: G06F12/16 ,  G06F11/20 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    Abstract: The memory has data lines (MDQii) which are connected to the local data lines located in the storage cell array. The data lines (MDQii) are compiled into groups (U1-U8) and at least one group, or discrete data lines of the groups, are formed by redundant data lines (MDQiiR), and are connected to the input/output (IO) lines leading out from the memory into the groups (IO1-IO4). A bus system arranged into at least two planes is provided and in which a first plane has available bus lines (Ai) which are connectable, on the one hand, to all IO lines (RWDii) and on the other hand, to the data lines (MDQii), and has a second plane of several separate part buses (B1-B4), whose bus lines (Bii) are connected on one side, to data lines (MDQii) of at least two groups of data lines (Qi), and on the other side, to the IO lines (RWDii) of one group (IO).

    Segmented word line architecture
    6.
    发明专利
    Segmented word line architecture 未知

    公开(公告)号：DE19944738A1

    公开(公告)日：2001-03-29

    申请号：DE19944738

    申请日：1999-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  PFEFFERL KARL-PETER

    IPC: G11C11/407 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C7/00

    Abstract: The master word line (WL0)is assigned an additional master word line (MWL1), to form master word line pairs in a memory cell field. The additional master word line can be decoded into several sub-word lines, as can the master word line. One master word line is connected via its sub-word lines (SWL) with memory banks of one logic state and the other master word line is connected via its sub-word lines with memory bands of the other logic state. Hence in word line direction, the memory banks of each logic state can be alternately accommodated. Between the master word lines and the sub word line a single address unit (5) is switched. Both master word lines have several sections of the sub word line assigned to them.

    8.
    发明专利
    未知

    公开(公告)号：DE102006019075B4

    公开(公告)日：2008-01-31

    申请号：DE102006019075

    申请日：2006-04-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PFEFFERL KARL-PETER

    IPC: G11C17/16 ,  G11C29/52

    Abstract: The circuit has a programmable circuit unit (10) comprising a programmable unit (F) e.g. fuse, where a programming state of the unit (F) is analyzed repeatedly, and a memory circuit (20) for storing a state of memory dependent on a programming state of the programmable unit. The memory circuit has inverter circuits (21, 22), where strengthening and/or weakening of n-channel and p-channel transistors (N2, P2, N4, P3) in the corresponding inverter circuits is realized by change of channel lengths and breadths of the transistors. An independent claim is also included for a method for operating an integrated circuit.

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