公开(公告)号：DE10250875A1

公开(公告)日：2003-05-15

申请号：DE10250875

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHLER THOMAS ,  LEHMANN GUNTHER

IPC: G11C29/38 ,  H01L21/66 ,  H01L21/8242

公开(公告)号：DE10250875B4

公开(公告)日：2014-09-25

申请号：DE10250875

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHLER THOMAS ,  LEHMANN GUNTHER

IPC: G11C29/24 ,  G11C29/38 ,  H01L21/8242

Abstract: Verfahren zum Konfigurieren einer Speichervorrichtung mit den Schritten: a) Sequenzielles Erhalten von jeweiligen Bitfehler-Informationen für jeweils N Gruppen einer vorbestimmten Anzahl K von Speicherstellen innerhalb der Speichervorrichtung (91), wobei K einen Kompressionsfaktor repräsentiert; b) Komprimieren der Bitfehler-Informationen der jeweiligen K Speicherstellen zum Erzeugen einer zu der jeweiligen Gruppe zugehörigen komprimierten Bitfehler-Information (91); c) Austauschen der Gruppen von Speicherstellen durch zugehörige Gruppen von redundanten Speicherschaltungen auf der Grundlage der komprimierten Bitfehler-Information (93); und d) Wiederholen der Schritte a) bis c) bis die Speichervorrichtung konfiguriert ist.

公开(公告)号：DE60302361T2

公开(公告)日：2006-08-03

申请号：DE60302361

申请日：2003-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER

IPC: G11C17/18 ,  H03K3/356 ,  G11C19/00 ,  G11C29/52 ,  H03K3/037 ,  H03K17/00

Abstract: A sequential fuse latch device comprises a plurality of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising a plurality of pointer latches, wherein each pointer latch is connected to at least one fuse latch, wherein the shift register controls a sequential operation of the plurality of fuse latches.

公开(公告)号：DE60302361D1

公开(公告)日：2005-12-22

申请号：DE60302361

申请日：2003-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER

IPC: H03K3/356 ,  G11C17/18 ,  G11C19/00 ,  H03K3/037 ,  H03K17/00 ,  G11C29/00

Abstract: A sequential fuse latch device comprises a plurality of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising a plurality of pointer latches, wherein each pointer latch is connected to at least one fuse latch, wherein the shift register controls a sequential operation of the plurality of fuse latches.

公开(公告)号：DE102004035273A1

公开(公告)日：2005-03-17

申请号：DE102004035273

申请日：2004-07-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  FRANKOWSKY GERD ,  TERLETZKI HARTMUD

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185

Abstract: A system and method is provided for controlling the impedance and current of an off chip driver circuit to match to load driven by the driver and for reducing noise and ringing in the off chip driver circuit. The driver comprises a pull up transistor for switching the output of the driver to a high-voltage, a pull down transistor for switching the output of the driver to a low voltage, a first current mirror transistor coupled to the pull up transistor for controlling the current transmitted to a load connected to the driver when the output of the driver is at the high-voltage, and a second current mirror transistor coupled to the pull down transistor for controlling the current transmitted to the load when the output of the driver is at the low voltage. In addition, the driver may include a first pre-driver providing a gate signal for the pull up transistor having a controlled slew rate and a second pre-driver providing a gate signal for the pull down transistor having a controlled slew rate.

公开(公告)号：DE102004010706A1

公开(公告)日：2004-10-21

申请号：DE102004010706

申请日：2004-03-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  FRANKOWSKY GERD

IPC: G11C5/14 ,  G11C11/4074 ,  G11C29/02 ,  G05F1/00

公开(公告)号：DE10304673A1

公开(公告)日：2003-08-28

申请号：DE10304673

申请日：2003-02-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANKOWSKY GERD ,  LEHMANN GUNTHER

IPC: G11C11/406

公开(公告)号：DE10261327A1

公开(公告)日：2003-08-07

申请号：DE10261327

申请日：2002-12-27

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： FRANKOWSKY GERD ,  HOKENMAIER WOLFGANG ,  HANSON DAVID R ,  LEHMANN GUNTHER

IPC: G11C7/18 ,  G11C11/4097 ,  G11C29/00

Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.