公开(公告)号：GB2259164B

公开(公告)日：1995-01-18

申请号：GB9216240

申请日：1992-07-30

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  NGUYEN CAU

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/14

Abstract: A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, and processor state data at the time of interruption. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The extended memory addressing limits are overridden when the CPU is interrupted by this added interrupt. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The extended memory addressing limits are restored when the CPU is restored by the RESUME instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with integrated extended memory addressing that will operate reliably in any operating environment, and be able to address the entire physical address space and have access to all system resources in a stand alone manner during the interrupt.

公开(公告)号：GB2264799A

公开(公告)日：1993-09-08

申请号：GB9305800

申请日：1993-03-19

Applicant: INTEL CORP

Inventor： REDDY CHANDRASHEKAR M ,  HIROSE SCOTT D ,  CHO SUNG-SOO ,  KARDACH JAMES P ,  FARRER STEVEN M ,  ROBERTS MEELING

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G11C11/401 ,  G11C11/406

Abstract: A power suspend mode activates a slow DRAM refresh in a computer system (10) with a limited source of power. The power suspend (100) mode reduces the power consumed by the computer system (10) while preserving the contents of memory. The cyclic refresh of DRAM (80) using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem (30) notifies the CPU (20) which sets control bits in the IO (30) subsystem and a video subsystem (40). The IO subsystem (30) then begins to generate a slow DRAM refresh pulse (91). Once the CPU (20) and video subsystem (40) sense the power suspend mode activation, the system memory (80) and video memory (50) are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem (30), the slow refresh clock (91) is terminated and the system memory (80) and video memory (50) are again refreshed using a normal faster clock.

公开(公告)号：DE102009058274A1

公开(公告)日：2010-07-01

申请号：DE102009058274

申请日：2009-12-14

Applicant: INTEL CORP

Inventor： KWA SEH W ,  KARDACH JAMES P

IPC: G06F3/14

Abstract: Einige Ausführungsformen beschreiben Techniken, die sich auf das Hybridgrafikanzeige-Power-Management beziehen. Bei einer Ausführungsform werden Daten, die einem oder mehreren Bildframes eines Video-Streams entsprechen, in einem lokalen Framebuffer gespeichert. Ein Anzeigegerät (z.B. ein LCD) kann dann basierend auf den gespeicherten Daten im lokalen Framebuffer oder einem Video-Stream eines Grafikcontrollers angesteuert werden. Weitere Ausführungsformen sind ebenfalls beschrieben.

公开(公告)号：DE60329355D1

公开(公告)日：2009-11-05

申请号：DE60329355

申请日：2003-08-14

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  CHINN GORDON ,  DURRANT RANDY ,  RAJAMANI KRISHNAN ,  MONROE ROBERT L

IPC: H04W72/12 ,  H04L12/28 ,  H04W88/06

Abstract: Methods and apparatus are disclosed for communicating via a radio channel to reduce radio frequency (RF) interference between transceiver systems within an electronic device.

公开(公告)号：GB2392526B

公开(公告)日：2005-04-06

申请号：GB0325168

申请日：2002-03-01

Applicant: INTEL CORP

Inventor： KARDACH JAMES P

IPC: H04B1/38 ,  G06F13/38 ,  H04L12/28 ,  H04L12/56

Abstract: A processor may perform real-time event processing of real-time events in a manner that enables a radio module equipped computer system to operate in accordance with a wireless communication protocol using host processor baseband processing. In accordance with one embodiment, the processor may perform real-time event processing by halting a process in response to receiving a real-time event, handling the event, then returning to the process. In accordance with another embodiment, the processor may perform real-time event processing on a non-symetric processing core integrated with a primary host processor core that shares the same L2 cache.

公开(公告)号：GB2393363B

公开(公告)日：2004-12-15

申请号：GB0325166

申请日：2002-03-01

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  SCHIFFER JEFFREY

IPC: G06F1/16 ,  H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08

Abstract: A radio module that meets FCC Limited Modular Approval including a wireless transceiver and a low-level baseband controller. Only a portion of the baseband associated with a wireless communication protocol is contained within the controller. The remainder of the baseband may be contained within a host computer system to which the module may be coupled such that, for one embodiment, the module may be selectively operated in accordance with one of multiple wireless communication protocols.

公开(公告)号：GB2392526A

公开(公告)日：2004-03-03

申请号：GB0325168

申请日：2002-03-01

Applicant: INTEL CORP

Inventor： KARDACH JAMES P

IPC: H04B1/38 ,  G06F13/38 ,  H04L12/28 ,  H04L12/56

Abstract: A processor (200) may perform real-time event processing of real-time events in a manner that enables a radio module equipped computer system to operate in accordance with a wireless communication protocol using host processor baseband processing. In accordance with one embodiment, the processor (200) may perform real-time event processing by halting a process in response to receiving a real-time event, handling the event, then returning to the process. In accordance with another embodiment, the processor (200) may perform real-time event processing on a non-symmetric processing core integrated with a primary host processor core (205) that shares the same L2 cache.(215).

公开(公告)号：DE69522595T2

公开(公告)日：2002-07-11

申请号：DE69522595

申请日：1995-01-06

Applicant: INTEL CORP

Inventor： RABE JEFFREY L ,  BHATT AJAY V ,  BOGIN ZOHAR ,  KARDACH JAMES P ,  SHAH NILESH V

IPC: G06F1/32

Abstract: A power consumption controller is described which switches a computer system between a fully operational mode and a responsive blow power mode. The computer system in the responsive low power mode is responsive to a computer network signal of a specified minimum duration.

公开(公告)号：AU6250798A

公开(公告)日：1998-11-27

申请号：AU6250798

申请日：1998-01-27

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  HORIGAN JOHN ,  EAKAMBARAM RAVI ,  NAKANISHI TOSAKU ,  CHUNG CHIH-HUNG ,  SENYK BORYS S

IPC: G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F1/18

Abstract: A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

公开(公告)号：SG48805A1

公开(公告)日：1998-05-18

申请号：SG1996001882

申请日：1995-01-06

Applicant: INTEL CORP

Inventor： RABE JEFFREY L ,  BOGIN ZOHAR ,  BHATT AJAY V ,  KARDACH JAMES P ,  SHAH NILESH V

IPC: G06F1/32

Abstract: A power consumption controller is described which switches a computer system between a fully operational mode and a responsive blow power mode. The computer system in the responsive low power mode is responsive to a computer network signal of a specified minimum duration.