公开(公告)号：DE19506435C2

公开(公告)日：2000-05-18

申请号：DE19506435

申请日：1995-02-24

Applicant: INTEL CORP

Inventor： COLWELL ROBERT P ,  FETTERMAN MICHAEL ALAN ,  GLEW ANDREW F ,  HINTON GLENN J ,  MARTELL ROBERT W ,  PAPWORTH DAVID B

IPC: G06F9/38 ,  G06F9/26

公开(公告)号：DE69420540T2

公开(公告)日：2000-02-10

申请号：DE69420540

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：SG48907A1

公开(公告)日：1998-05-18

申请号：SG1996003661

申请日：1994-08-31

Applicant: INTEL CORP

Inventor： PAPWORTH DAVID B ,  HINTON GLEN J ,  FETTEEMAN MICHAEL ALAIN ,  COLWELL ROBERT P ,  GLEW ANDREW F

IPC: G06F9/38

Abstract: A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

公开(公告)号：GB2284493B

公开(公告)日：1998-04-01

申请号：GB9417470

申请日：1994-08-31

Applicant: INTEL CORP

Inventor： PAPWORTH DAVID B ,  HINTON GLEN J ,  FETTERMAN MICHAEL ALAN ,  COLWELL ROBERT P ,  GLEW ANDREW F

IPC: G06F9/38

Abstract: A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

公开(公告)号：DE19506435A1

公开(公告)日：1995-09-14

申请号：DE19506435

申请日：1995-02-24

Applicant: INTEL CORP

Inventor： COLWELL ROBERT P ,  FETTERMAN MICHAEL ALAN ,  GLEW ANDREW F ,  HINTON GLENN J ,  MARTELL ROBERT W ,  PAPWORTH DAVID B

IPC: G06F9/38 ,  G06F9/26

Abstract: Pipeline lengthening in functional units 31, 32 likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage 60 to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

公开(公告)号：GB2287109A

公开(公告)日：1995-09-06

申请号：GB9500255

申请日：1995-01-06

Applicant: INTEL CORP

Inventor： COLWELL ROBERT P ,  FETTERMAN MICHAEL ALAN ,  GLEW ANDREW F ,  HINTON GLENN J ,  PAPWORTH DAVID B

IPC: C23C14/35 ,  C23C16/511 ,  G06F9/38 ,  G06F15/76

Abstract: Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.

公开(公告)号：GB2285526A

公开(公告)日：1995-07-12

申请号：GB9425726

申请日：1994-12-20

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F9/32

Abstract: A Branch Target Buffer Circuit in a computer predicts branch instructions in a stream of computer instructions. The Branch Target Buffer Circuit 40 uses a Branch Target Buffer Cache 41 that stores information about previously executed branch instructions. The information stored is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit 30 in the computer fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the pointer, Circuit 40 looks in the Cache 41 to see if any of the instructions in the block is a branch instruction. If it is, circuit 40 informs the Instruction Fetch Unit about the upcoming branch instruction and the branch outcome is predicted. The cache may be a set-associative one.