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    QOS based binary translation and application streaming
    1.
    发明专利
    QOS based binary translation and application streaming 未知

    公开(公告)号：GB2514222A

    公开(公告)日：2014-11-19

    申请号：GB201404232

    申请日：2014-03-11

    Applicant: INTEL CORP

    Inventor： MUTHIAH BHARATH ,  RASH WILLIAM BILL ,  HINTON GLENN J ,  DIXON MARTIN G ,  HAHN SCOTT D ,  PAPWORTH DAVID B

    IPC: G06F9/455 ,  G06F9/45

    Abstract: A system comprises a server which includes a processor having a first instruction set, wherein the server translates binary code having a second instruction set into an executable binary having the first instruction set. The server then executes the binary to generate a frame of rendered output, and this is transmitted to and displayed on a client device. The frame may be encoded into a media format before transmission. The translation, rendering, encoding and delivery process may be governed by Quality of Service (QoS) criteria, such as resolution, location, type and decode capabilities of the client device. A processor of the client device may have the second instruction set, and may request an application from the server. The binary translation may occur within a virtual machine.

    2.
    发明专利
    未知

    公开(公告)号：AT184407T

    公开(公告)日：1999-09-15

    申请号：AT94307771

    申请日：1994-10-21

    Applicant: INTEL CORP

    Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

    IPC: G06F9/38

    Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

    3.
    发明专利
    未知

    公开(公告)号：DE19506990A1

    公开(公告)日：1995-09-07

    申请号：DE19506990

    申请日：1995-02-28

    Applicant: INTEL CORP

    Inventor： COLWELL ROBERT P ,  FETTERMAN MICHAEL A ,  GLEW ANDREW F ,  HINTON GLENN J ,  PAPWORTH DAVID B

    IPC: C23C14/35 ,  C23C16/511 ,  G06F9/38 ,  G06F9/28

    Abstract: A bypassing scheme for increasing the throughput of instructions executed by a complex microprocessor. The functional units within the execution data path are provided with bypassing multiplexer logic which allows the result data from an executed instruction to be immediately provided as source data to a dependent instruction at a different or the same execution unit. By providing comprehensive bypassing between execution units in the data path, instruction execution throughput can be maximized.

    tradução binária e transmissão em fluxo de aplicativo baseados em qos
    5.
    发明专利
    tradução binária e transmissão em fluxo de aplicativo baseados em qos 未知

    公开(公告)号：BR102014006116A2

    公开(公告)日：2015-11-03

    申请号：BR102014006116

    申请日：2014-03-14

    Applicant: INTEL CORP

    Inventor： MUTHIAH BHARATH ,  PAPWORTH DAVID B ,  HINTON GLENN J ,  DIXON MARTIN G ,  HAHN SCOTT D ,  RASH WILLIAM BILL

    IPC: H04L29/06

    Abstract: traduçáo binária e transmissão em fluxo de aplicativo baseados em qos. em uma modalidade, a tradução binária do lado do servidor com base em critérios de qualidade de serviço (qos) e a execução de aplicativos é realizada em múltiplos servidores utilizando tradução e execução distribuídas tanto em um ambiente de execução virtualizado como em um nativo. os aplicativos traduzidos são executados para gerar dados de exibição de saida, os dados de exibição de saída sendo codificados em um formato de midia adequado para streaming de video, e o fluxo de vídeo sendo disponibilizado através de uma rede para um dispositivo de cliente. em uma modalidade, um ou mais processadores gráficos auxiliam os processadores centrais dos servidores, acelerando a renderização de saída do aplicativo, e um codificador de mídia codifica a saída do aplicativo em um formato de mídia

    Pipelined processing of instructions
    10.
    发明专利
    Pipelined processing of instructions 未知

    公开(公告)号：GB2287111A

    公开(公告)日：1995-09-06

    申请号：GB9500762

    申请日：1995-01-16

    Applicant: INTEL CORP

    Inventor： HINTON GLENN J ,  PAPWORTH DAVID B ,  GLEW ANDREW F ,  FETTERMAN MICHAEL ALAN ,  COLWELL ROBERT P

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G09F13/04 ,  G06F15/76

    Abstract: A pipelined method for executing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages.

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