公开(公告)号：US11416165B2

公开(公告)日：2022-08-16

申请号：US16160482

申请日：2018-10-15

Applicant: INTEL CORPORATION

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1081 ,  G06N3/04 ,  G06F12/0802 ,  G06N3/063 ,  G06F12/0875 ,  G06F12/0897

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

公开(公告)号：US11380684B2

公开(公告)日：2022-07-05

申请号：US16145817

申请日：2018-09-28

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Willy Rachmady ,  Anh Phan ,  Ehren Mannebach ,  Abhishek Sharma ,  Patrick Morrow ,  Hui Jae Yoo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

公开(公告)号：US11245038B2

公开(公告)日：2022-02-08

申请号：US16490503

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Lee

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66

Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

公开(公告)号：US11164809B2

公开(公告)日：2021-11-02

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US11101376B2

公开(公告)日：2021-08-24

申请号：US16613751

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L31/00 ,  H01L29/76 ,  H01L21/02 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.

公开(公告)号：US11011550B2

公开(公告)日：2021-05-18

申请号：US16461697

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Van Le ,  Abhishek Sharma ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack Kavalieros

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/22 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/49

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

公开(公告)号：US20210064076A1

公开(公告)日：2021-03-04

申请号：US16557860

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Gururaj Shamanna ,  Mitesh Goyal ,  Jagadeesh Salaka ,  Purna C. Nayak ,  Abhishek Sharma ,  Harishankar Sahu

IPC: G06F1/12 ,  H03K19/20 ,  H03K3/037

Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.

公开(公告)号：US10831446B2

公开(公告)日：2020-11-10

申请号：US16145569

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Abhishek Sharma ,  Ian A. Young

IPC: G06F7/544 ,  G06F17/16 ,  G06F7/501 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063

Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit×n-bit multiplications.

公开(公告)号：US20200312839A1

公开(公告)日：2020-10-01

申请号：US16367144

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek Sharma ,  Brian Doyle ,  Ravi Pillarisetty ,  Willy Rachmady

IPC: H01L27/06 ,  H01L23/528 ,  H01L29/267 ,  H01L21/02

Abstract: IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

公开(公告)号：US20190393224A1

公开(公告)日：2019-12-26

申请号：US16488231

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Van Le

IPC: H01L27/108 ,  G11C11/408 ,  H01L29/786 ,  H01L23/528 ,  H01L29/24 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  H01L49/02 ,  H01L29/66

Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.