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31.发明授权公开(公告)号：US12175589B2
公开(公告)日：2024-12-24
申请号：US18228777
申请日：2023-08-01
Applicant: INTEL CORPORATION
Inventor： Ingo Wald , Carsten Benthin , Sven Woop
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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32.发明公开公开(公告)号：US20240282045A1
公开(公告)日：2024-08-22
申请号：US18589239
申请日：2024-02-27
Applicant: Intel Corporation
Inventor： Sven Woop , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Joshua Barczak , Saikat Mandal
CPC classification number: G06T15/06 , G06T15/005 , G06T2210/21
Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.
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公开(公告)号：US11989818B2
公开(公告)日：2024-05-21
申请号：US17533531
申请日：2021-11-23
Applicant: INTEL CORPORATION
Inventor： Carsten Benthin , Sven Woop
Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.
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公开(公告)号：US11915459B2
公开(公告)日：2024-02-27
申请号：US17740754
申请日：2022-05-10
Applicant: INTEL CORPORATION
Inventor： Carson Brownlee , Carsten Benthin , Joshua Barczak , Kai Xiao , Michael Apodaca , Prasoonkumar Surti , Thomas Raoux
CPC classification number: G06T9/40 , G06T1/60 , G06T15/06 , G06T15/20 , G06T2210/21
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US11915369B2
公开(公告)日：2024-02-27
申请号：US16819120
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Carsten Benthin , Sven Woop
CPC classification number: G06T17/10 , G06F7/24 , G06T1/20 , G06T15/005 , G06T15/06 , G06T15/08 , G06T17/205
Abstract: Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.
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Patent Agency Ranking
公开(公告)号：US11887243B2
公开(公告)日：2024-01-30
申请号：US17533341
申请日：2021-11-23
Applicant: INTEL CORPORATION
Inventor： Karthik Vaidyanathan , Sven Woop , Carsten Benthin
CPC classification number: G06T15/06 , G06T1/60 , G06T9/40 , G06T17/005 , G06T2210/12 , G06T2210/21
Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.
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37.发明授权公开(公告)号：US11769290B2
公开(公告)日：2023-09-26
申请号：US17557968
申请日：2021-12-21
Applicant: Intel Corporation
Inventor： Carsten Benthin , Gabor Liktor
CPC classification number: G06T15/06 , G06T15/005
Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tessellate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.
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公开(公告)号：US20230090973A1
公开(公告)日：2023-03-23
申请号：US17480528
申请日：2021-09-21
Applicant: Intel Corporation
Inventor： Joydeep Ray , Abhishek R. Appu , Timothy R. Bauer , James Valerio , Weiyu Chen , Subramaniam Maiyuran , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Sven Woop , Jiasheng Chen
Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.
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公开(公告)号：US11568591B2
公开(公告)日：2023-01-31
申请号：US16996208
申请日：2020-08-18
Applicant: INTEL CORPORATION
Inventor： Karthik Vaidyanathan , Michael Apodaca , Thomas Raoux , Carsten Benthin , Kai Xiao , Carson Brownlee , Joshua Barczak
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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公开(公告)号：US11501484B2
公开(公告)日：2022-11-15
申请号：US17032964
申请日：2020-09-25
Applicant: INTEL CORPORATION
Inventor： Michael Apodaca , Carsten Benthin , Kai Xiao , Carson Brownlee , Timothy Rowley , Joshua Barczak , Travis Schluessler
Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
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