公开(公告)号：US09793163B2

公开(公告)日：2017-10-17

申请号：US14912036

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Florian Gstrein ,  Richard E. Schenker ,  Paul A. Nyhus ,  Charles H. Wallace ,  Hui Jae Yoo

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.

公开(公告)号：US20240234579A1

公开(公告)日：2024-07-11

申请号：US18444520

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L29/66 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US12020929B2

公开(公告)日：2024-06-25

申请号：US16454568

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L23/498 ,  H01L21/02 ,  H01L25/065

CPC classification number: H01L21/02532 ,  H01L21/02472 ,  H01L23/49827 ,  H01L25/0657

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.

公开(公告)号：US12002754B2

公开(公告)日：2024-06-04

申请号：US16911879

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Kevin L. Lin

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/32 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228

Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.

公开(公告)号：US11812599B2

公开(公告)日：2023-11-07

申请号：US17670248

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Noriyuki Sato ,  Sarah Atanasov ,  Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Hui Jae Yoo ,  Van H. Le

IPC: G11C8/00 ,  H10B12/00 ,  H01L27/12 ,  G11C11/4096

CPC classification number: H10B12/00 ,  G11C11/4096 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1266

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US11798838B2

公开(公告)日：2023-10-24

申请号：US16358520

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Rishabh Mehandru ,  Hui Jae Yoo ,  Patrick Morrow ,  Kevin Lin

IPC: H01L21/768 ,  H01L21/683 ,  H01L21/762 ,  H01L23/31 ,  H01L29/417

CPC classification number: H01L21/7682 ,  H01L21/6836 ,  H01L21/76256 ,  H01L23/3171 ,  H01L29/41775 ,  H01L2221/68381

Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230084611A1

公开(公告)日：2023-03-16

申请号：US17471295

申请日：2021-09-10

Applicant: INTEL CORPORATION

Inventor： Noriyuki Sato ,  Abhishek A. Sharma ,  Van H. Le ,  Hui Jae Yoo

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/66

Abstract: Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor. In such 2T capacitorless memory cells, a first transistor may be referred to a write transistor, and a second transistor may be a read transistor. The first transistor may be a three-terminal device having two S/D terminals and a gate terminal, while the second transistor may be a four-terminal device having two S/D terminals and two gate terminals.

公开(公告)号：US11605592B2

公开(公告)日：2023-03-14

申请号：US16232524

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Kevin Lin ,  Kevin O'Brien ,  Hui Jae Yoo

IPC: H01L23/532 ,  H01L43/10 ,  H01L43/12 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3213

Abstract: A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.

公开(公告)号：US20230067765A1

公开(公告)日：2023-03-02

申请号：US17409877

申请日：2021-08-24

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Noriyuki Sato ,  Van H. Le ,  Sarah Atanasov ,  Hui Jae Yoo ,  Bernhard Sell ,  Pei-hua Wang ,  Travis W. Lajoie ,  Chieh-Jen Ku ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L23/00 ,  H01L25/065

Abstract: IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

公开(公告)号：US11569238B2

公开(公告)日：2023-01-31

申请号：US16222940

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Kimin Jun ,  Hui Jae Yoo ,  Patrick Morrow ,  Sean T. Ma ,  Ahn Phan ,  Abhishek Sharma ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L23/528 ,  H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/417 ,  H01L29/51

Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.