公开(公告)号：US20250105156A1

公开(公告)日：2025-03-27

申请号：US18473479

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Bohan Shan ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual TGVs to individual conductive pathways. In some embodiments, the interconnects include solder or liquid metal ink. In some embodiments, the interconnects include metal-metal bonds and dielectric-dielectric bonds.

公开(公告)号：US20250096053A1

公开(公告)日：2025-03-20

申请号：US18470645

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Bohan Shan ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.

公开(公告)号：US20250079266A1

公开(公告)日：2025-03-06

申请号：US18456615

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy Ecton

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a blind cavity between a first surface and a second opposing surface; a bridge die in the blind cavity, the blind cavity being open towards the first surface; and a plurality of integrated circuit (IC) dies coupled to the first surface and to the bridge die. The blind cavity has a floor and a plurality of sidewalls, at least one sidewall is at an obtuse angle to the floor, and the at least one sidewall is patterned with conductive traces.

公开(公告)号：US12191161B2

公开(公告)日：2025-01-07

申请号：US17132282

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Oladeji Fadayomi ,  Jeremy Ecton ,  Oscar Ojeda

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/498

Abstract: An integrated circuit device, comprising a substrate comprising a dielectric material and a conductor on or within the dielectric material of the substrate. The conductor comprises a first portion comprising a first sloped sidewall, wherein a first base width of the first portion is greater than a first top width of the first portion. The conductor also comprises a second portion over the first portion, the second portion comprising a second sloped sidewall, wherein a second base width of the upper portion is greater than both a second top width of the second portion and the first top width of the first portion.

公开(公告)号：US20250006570A1

公开(公告)日：2025-01-02

申请号：US18883851

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Srinivas Venkata Ramanuja Pietambaram ,  Jeremy Ecton ,  Brandon Christian Marin

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: Glass cores including multiple layers and related methods are disclosed. An apparatus disclosed herein includes a printed circuit board and an integrated circuit package coupled to the printed circuit board, the integrated circuit package including a die and a glass core including a first layer having a first coefficient of thermal expansion and a second layer having a second coefficient of thermal expansion different than the first coefficient of thermal expansion.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20240194608A1

公开(公告)日：2024-06-13

申请号：US18080612

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Gang Duan ,  Rahul Manepalli ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L2221/68359

Abstract: An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

公开(公告)号：US20240178162A1

公开(公告)日：2024-05-30

申请号：US18060125

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2223/6616

Abstract: An integrated circuit (IC) package substrate including a glass core having a cavity filter structure, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include a core made of glass, and the core including a first core portion having a first surface and a trench and a ridge in the first surface, the trench and the ridge lined with a conductive material; and a second core portion having a second surface, the second surface lined with the conductive material, wherein the first surface of the first core portion is physically coupled to the second surface of the second core portion forming a cavity filter structure.

公开(公告)号：US20240176070A1

公开(公告)日：2024-05-30

申请号：US18059057

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Changhua Liu ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: G02B6/12 ,  H01L25/16

CPC classification number: G02B6/12004 ,  H01L25/167

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is coupled to the surface of the core by optical glue or by fusion bonding; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the core and the first optical component.

公开(公告)号：US20240079339A1

公开(公告)日：2024-03-07

申请号：US17929045

申请日：2022-09-01

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L23/481 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.