公开(公告)号：WO2017205002A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/030323

申请日：2017-04-30

Applicant: INTEL CORPORATION

Inventor： SEILER, Larry ,  SURTI, Prasoonkumar ,  NAVALE, Aditya

IPC: G06T9/00 ,  G06T1/20 ,  G06T1/60

Abstract: Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.

Abstract translation: 这里描述的是计算机图形技术，以促进对包括纹理图的存储器块进行有效且高效的存储器处理。 更具体地说，本文描述的一个或多个实施方式有利于对存储器资源（包括纹理图）的空数据支持的存储器的分层无损压缩。 更特别地，这里描述的一个或多个实施方式促进了用于无损压缩的元数据的使用以及对于平铺资源的空编码的支持。 该技术还允许使用快速清除压缩方法，其中元数据指定整个访问应返回一些指定的明确值。

公开(公告)号：WO2014182469A1

公开(公告)日：2014-11-13

申请号：PCT/US2014/035453

申请日：2014-04-25

Applicant: INTEL CORPORATION ,  AKENINE-MOLLER, Tomas, G. ,  SURTI, Prasoonkumar ,  MUNKBERG, Carl, J.

Inventor： AKENINE-MOLLER, Tomas, G. ,  SURTI, Prasoonkumar ,  MUNKBERG, Carl, J.

IPC: G06T1/00 ,  G06T5/00

CPC classification number: G09G3/2003 ,  G06T11/20 ,  G06T11/40 ,  G06T2200/12

Abstract: Techniques related to graphics rendering including techniques for improved multi -sampling anti-aliasing compression by use of unreachable bit combinations are described. A computer-implemented method for providing anti-aliasing in graphics rendering comprising determining bit combinations for individual pixels of a tile of pixels and transforming at least one bit combination of the bit combinations to an unreachable bit combination.

Abstract translation: 描述与图形渲染相关的技术，包括通过使用不可达位组合来改进多采样抗混叠压缩的技术。 一种用于在图形渲染中提供抗锯齿的计算机实现的方法，包括确定像素块的各个像素的比特组合，并将比特组合的至少一个比特组合变换为不可达比特组合。

公开(公告)号：WO2022039869A1

公开(公告)日：2022-02-24

申请号：PCT/US2021/042381

申请日：2021-07-20

Applicant: INTEL CORPORATION

Inventor： WOOP, Sven ,  DOYLE, Michael J. ,  KOTHANDARAMAN, Sreenivas ,  VAIDYANATHAN, Karthik ,  APPU, Abhishek R. ,  BENTHIN, Carsten ,  SURTI, Prasoonkumar ,  GRÜEN, Holger ,  JUNKINS, Stephen ,  LAKE, Adam ,  ALFIERI, Bret G. ,  LIKTOR, Gabor ,  BARCZAK, Joshua ,  LEE, Won-Jong

IPC: G06T15/50 ,  G06T15/60

Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

公开(公告)号：WO2020190812A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022850

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： RANGANATHAN, Vasanth ,  APPU, Abhishek R. ,  ASHBAUGH, Ben ,  DOYLE, Peter ,  FLIFLET, Brandon ,  HUNTER, Arthur ,  INSKO, Brent ,  JANUS, Scott ,  KOKER, Altug ,  NAVALE, Aditya ,  RAY, Joydeep ,  SINHA, Kamal ,  STRIRAMASSARMA, Lakshminarayanan ,  SURTI, Prasoonkumar ,  VALERIO, James

IPC: G06F9/50

Abstract: Embodiments are generally directed to compute optimization in graphics processing. An embodiment of an apparatus includes one or more processors including a multi-tile graphics processing unit (GPU) to process data, the multi-tile GPU including multiple processor tiles; and a memory for storage of data for processing, wherein the apparatus is to receive compute work for processing by the GPU, partition the compute work into multiple work units, assign each of multiple work units to one of the processor tiles, and process the compute work using the processor tiles assigned to the work units.

公开(公告)号：WO2020190808A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022846

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： RAY, Joydeep ,  JANUS, Scott ,  GEORGE, Varghese ,  MAIYURAN, Subramaniam ,  KOKER, Altug ,  APPU, Abhishek ,  SURTI, Prasoonkumar ,  RANGANATHAN, Vasanth ,  ANDREI, Valentin ,  GARG, Ashutosh ,  HAREL, Yoav ,  HUNTER, JR., Arthur ,  KIM, SungYe ,  MACPHERSON, Mike ,  OULD-AHMED-VALL, Elmoustapha ,  SADLER, William ,  STRIRAMASSARMA, Lakshminarayanan ,  VEMULAPALLI, Vikranth

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：WO2020190776A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022763

申请日：2020-03-13

Applicant: INTEL CORPORATION

Inventor： JANUS, Scott ,  KRISHNAN, Vidhya ,  NEMIROFF, Daniel ,  KUMAR, Gaurav ,  HUNTER, Arthur ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  STRIRAMASSARMA, Lakshminarayanan ,  SURTI, Prasoonkumar

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/14 ,  G06F21/10 ,  H04L29/06

Abstract: An apparatus to facilitate synchronizing encrypted workloads across multiple graphics processing units is disclosed. The apparatus includes a memory and one or more processors of the plurality of GPUs, the one or more processors communicably coupled to the memory. The one or more processors are to receive a license associated with the encrypted workload, the license comprising a private content key corresponding to a secure compute application generating the encrypted workload, encrypt the private content key with a first key to generate a session key, the first key shared among graphic security controllers (GSCs) of the plurality of GPUs, and inject the session key into a region of the memory that is shared among the plurality of GPUs.

公开(公告)号：WO2020190456A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/019532

申请日：2020-02-24

Applicant: INTEL CORPORATION

Inventor： GEORGE, Varghese ,  KOKER, Altug ,  ANANTARAMAN, Aravindh ,  MAIYURAN, Subramaniam ,  KIM, SungYe ,  ANDREI, Valentin ,  OULD-AHMED-VALL, Elmoustapha ,  RAY, Joydeep ,  APPU, Abhishek R. ,  GALOPPO VON BORRIES, Nicolas C. ,  SURTI, Prasoonkumar ,  MACPHERSON, Mike

IPC: G06F15/78 ,  G06F15/17

Abstract: Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.

公开(公告)号：WO2018071121A1

公开(公告)日：2018-04-19

申请号：PCT/US2017/051034

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： DASGUPTA, Subhajit ,  APPU, Abhishek ,  SURTI, Prasoonkumar

IPC: G06F12/0811

CPC classification number: G06T1/60 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0893 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/455

Abstract: Methods and apparatus relating to techniques to improve/optimize latency and bandwidth efficiency for read modify write operations when a read operation is requested to a partially modified write only cacheline are described. In an embodiment, a first cache stores data from one or more cachelines of a second cache in response to a read hit write only operation (e.g., instead of sending the data to main memory). Write accumulate logic merges the stored data with one or more write operations. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了当向读取操作被请求到部分修改的只写高速缓存行时，用于改进/优化读取修改写入操作的等待时间和带宽效率的技术的方法和设备。 在一个实施例中，响应于读命中只写操作（例如，而不是将数据发送到主存储器），第一高速缓存存储来自第二高速缓存的一个或多个高速缓存行的数据。 写入累积逻辑将存储的数据与一个或多个写入操作合并。 其他实施例也被公开和要求保护。

公开(公告)号：WO2016200493A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/028455

申请日：2016-04-20

Applicant: INTEL CORPORATION

Inventor： PODDAR, Bimal ,  SURTI, Prasoonkumar ,  SATHE, Rahul, P.

IPC: G06T1/20 ,  G06T15/04 ,  G06T11/40

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/04 ,  G06T15/506 ,  G06T19/20 ,  G06T2200/04 ,  G06T2200/28 ,  G06T2210/62

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

Abstract translation: 实施例提供了一种包括渲染逻辑的图形处理装置，用于检测将导致具有与初始清除颜色值相同的数据的帧缓冲器的渲染操作，并将这种渲染操作变形为通常对初始清除帧缓冲器而进行的优化。

公开(公告)号：WO2014189730A1

公开(公告)日：2014-11-27

申请号：PCT/US2014/037953

申请日：2014-05-14

Applicant: INTEL CORPORATION ,  AKENINE-MOLLER, Tomas G. ,  PIAZZA, Thomas A. ,  SURTI, Prasoonkumar

Inventor： AKENINE-MOLLER, Tomas G. ,  PIAZZA, Thomas A. ,  SURTI, Prasoonkumar

IPC: G06T1/00 ,  H04N9/64

CPC classification number: G06T5/002 ,  G06T9/00 ,  G06T11/40 ,  G06T15/503

Abstract: Techniques related to graphic rendering including lossy color merge for multi-sampling anti-aliasing compression are discussed. A method for providing anti-aliasing in graphic rendering comprising determining two or more colors associated with a plurality of color samples of a pixel; determining a first color of the two or more colors and a second color of the two or more colors are substantially similar; merging the first color and the second color to form a merged color; and replacing the first color and the second color with the merged color.

Abstract translation: 讨论了与图形渲染相关的技术，包括用于多采样抗锯齿压缩的有损颜色合并。 一种用于在图形渲染中提供抗锯齿的方法，包括确定与像素的多个颜色样本相关联的两个或多个颜色; 确定两种或更多种颜色的第一颜色和两种或更多种颜色的第二颜色基本相似; 合并第一种颜色和第二种颜色以形成合并的颜色; 并用合并的颜色替换第一颜色和第二颜色。