公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

公开(公告)号：US20240063100A1

公开(公告)日：2024-02-22

申请号：US17889229

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Mohammad Mamunur RAHMAN ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Kemal AYGÜN ,  Cemil GEYIK

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/49811

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.

公开(公告)号：US20230420357A1

公开(公告)日：2023-12-28

申请号：US17848624

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Sameer PAITAL

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/0217 ,  H01L21/486 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420322A1

公开(公告)日：2023-12-28

申请号：US17848615

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Yi YANG ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Darko GRUJICIC ,  Marcel WALL

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L23/3142 ,  H01L23/49827 ,  H01L23/49513

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an organic adhesion promoter layer on the surface of a copper trace to reduce delamination between a dielectric material and the surface of the copper trace, and to facilitate a smooth surface interface between the surface of the copper trace and of a copper feature, such as a copper-filled via, placed on the surface of the copper trace. The smooth surface interface reduces insertion loss and enables routing of higher frequency signals on a package, and does not require roughing of the copper trace in order to adhere to the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230361043A1

公开(公告)日：2023-11-09

申请号：US18224504

申请日：2023-07-20

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5385 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L24/13 ,  H01L2224/73265 ,  H01L2224/73204 ,  H01L2924/1434 ,  H01L2224/92125 ,  H01L23/5383 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2224/131 ,  H01L2224/32225 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/1511 ,  H01L2924/15747 ,  H01L2924/1579

Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US20230089093A1

公开(公告)日：2023-03-23

申请号：US17482804

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Krishna BHARATH ,  Bharat PENMECHA ,  Anderw COLLINS ,  Kaladhar RADHAKRISHNAN ,  Sriram SRINIVASAN

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a plug is formed through the core, where the plug comprises a magnetic material. In an embodiment, an inductor is around the plug. In an embodiment, first layers are over the core, wherein where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.

公开(公告)号：US20210358872A1

公开(公告)日：2021-11-18

申请号：US17387836

申请日：2021-07-28

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI ,  Kristof Kuwawi DARMAWIKARTA ,  Robert Alan MAY ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING

IPC: H01L23/66 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.

公开(公告)号：US20190206786A1

公开(公告)日：2019-07-04

申请号：US15857454

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Sandeep GAAN ,  Srinivas V. PIETAMBARAM ,  Sameer R. PAITAL

IPC: H01L23/50 ,  H01L23/498 ,  H01L49/02 ,  H01L23/64 ,  H01L21/48

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L23/49822 ,  H01L28/20 ,  H01L28/40

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first surface, one or more second conductive contacts on a second surface opposite the first surface, a dielectric layer between the first and the second surfaces, and an embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250105119A1

公开(公告)日：2025-03-27

申请号：US18373848

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Yuqin LI ,  Jesse JONES ,  Sandrine LTEIF ,  Srinivas V. PIETAMBARAM ,  Suresh Tanaji NARUTE ,  Pramod MALATKAR ,  Gang DUAN ,  Khaled AHMED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15

Abstract: Embodiments disclosed herein include glass cores with vias that are lined by a self-healing liner. In an embodiment, an apparatus comprises a substrate that comprises a solid glass layer with an opening through a thickness of the substrate. In an embodiment, a liner is in contact with a sidewall of the opening, where the liner comprises a polymer matrix with capsules distributed through the polymer matrix. In an embodiment, each capsule comprises a shell, and a core within the shell. In an embodiment, the core comprises an organic material. In an embodiment, a via is in the opening and in contact with the liner, and the via is electrically conductive.

公开(公告)号：US20240332125A1

公开(公告)日：2024-10-03

申请号：US18128848

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Clay ARRINGTON ,  Bohan SHAN ,  Haobo CHEN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying XU ,  Bai NIE

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/24 ,  H01L23/498

CPC classification number: H01L23/3737 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/24 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a first layer and a second layer over the first layer. In an embodiment, the second layer comprises a dielectric material including sulfur. In an embodiment, fillers are within the second layer. In an embodiment, the fillers have a volume fraction that is less than approximately 0.2.