公开(公告)号：US20150104907A1

公开(公告)日：2015-04-16

申请号：US14570785

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/00 ,  H01L23/34 ,  H01L21/56

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract translation: 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。

公开(公告)号：US20150011050A1

公开(公告)日：2015-01-08

申请号：US14495396

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20240329301A1

公开(公告)日：2024-10-03

申请号：US18130052

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Ravindranath V. Mahajan ,  Chia-Pin Chiu

IPC: G02B6/12

CPC classification number: G02B6/12004

Abstract: A substrate for a multi-chip package includes at least one photonic integrated circuit (PIC) interposer mounted in a cavity in a first major surface. Each PIC interposer is configured to electrically connect with, or optically couple to, a plurality of integrated circuit devices. The substrate further includes at least one optical coupler that is optically coupled to the PIC interposer.

公开(公告)号：US20240319437A1

公开(公告)日：2024-09-26

申请号：US18189844

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Julia Chiu ,  Chia-Pin Chiu ,  Kaveh Hosseini ,  Madhubanti Chatterjee

IPC: G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/136

Abstract: A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.

公开(公告)号：US12094800B2

公开(公告)日：2024-09-17

申请号：US16721809

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Jin Yang ,  Chia-Pin Chiu ,  Peng Li ,  Deepak Goyal

IPC: H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538

CPC classification number: H01L23/3675 ,  H01L23/3121 ,  H01L23/3185 ,  H01L25/0652 ,  H01L25/18 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/3738 ,  H01L23/538 ,  H01L24/32 ,  H01L2224/32225

Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

公开(公告)号：US11984396B2

公开(公告)日：2024-05-14

申请号：US18089213

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5226 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/05 ,  H01L24/13 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/05541 ,  H01L2924/206 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20230341638A1

公开(公告)日：2023-10-26

申请号：US17725018

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Omkar G. Karhade ,  Kaveh Hosseini

IPC: G02B6/42

CPC classification number: G02B6/4212 ,  G02B6/428 ,  G02B6/4273 ,  G02B6/4206

Abstract: Variations in a thermal structure for an open cavity photonic integrated circuit (OCPIC) having an MRR. The structure includes an air trench in fluid communication with an air cavity that is located under the MRR. The air trench is a gap/opening in the oxide that encircles at least a portion of the MRR and extends outward radially therefrom, with a consistent width, to a diameter D1. An oxide cladding is not removed in areas that are used for metal traces and routing. The structure is characterized by straight walls along the air trench. The structure has a lower diameter D2, measured at a bottom/floor of the air cavity. In various embodiments, D2 is substantially equal to D1.

公开(公告)号：US20230194791A1

公开(公告)日：2023-06-22

申请号：US17557630

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar Karhade ,  Kaveh Hosseini ,  Chia-Pin Chiu

IPC: G02B6/36 ,  G02B3/00 ,  H01L25/16

CPC classification number: G02B6/3616 ,  G02B3/0087 ,  H01L25/167 ,  G02B2003/0093

Abstract: An electronic device may include a photonic integrated circuit (PIC) coupled with a substrate. The PIC may communicate a photonic signal with one or more optical fibers. The PIC may process the photonic signal into an electronic signal. The electronic device may include an electronic integrated circuit (EIC) coupled with the substrate. The EIC may communicate with the PIC. The EIC may transmit the electronic signal to the PIC. The EIC may receive the electronic signal from the PIC. The electronic device may include a lens assembly. The lens assembly may include at least one gradient refractive index (GRIN) lens.

公开(公告)号：US11652020B2

公开(公告)日：2023-05-16

申请号：US16425264

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Robert Sankman

IPC: H05K1/18 ,  H01L23/367 ,  H01L23/00 ,  H01L23/42 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H05K1/14 ,  H01L25/00

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L23/42 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H05K1/144 ,  H05K1/181 ,  H01L2224/16227 ,  H05K2201/042 ,  H05K2201/10378 ,  H05K2201/10424

Abstract: Integrated circuit assemblies, electronic systems, and methods for fabricating the same are disclosed. An integrated circuit assembly is formed by thermally contacting at least two integrated circuit packages to opposite sides of a shared heat dissipation device. In one embodiment, the at least two integrated circuit packages are electrically attached to an electronic card to form an intermediate integrated circuit assembly. In a further embodiment, the integrated circuit assembly includes at least one intermediate integrated circuit assembly electrically attached to an electronic board.

公开(公告)号：US11521914B2

公开(公告)日：2022-12-06

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.