公开(公告)号：US20220157706A1

公开(公告)日：2022-05-19

申请号：US17665315

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20220059476A1

公开(公告)日：2022-02-24

申请号：US17518504

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Sujit SHARAN ,  Jianyong XIE

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L21/48 ,  H01L25/16

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US20210125942A1

公开(公告)日：2021-04-29

申请号：US17143142

申请日：2021-01-06

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20200013734A1

公开(公告)日：2020-01-09

申请号：US16576520

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20190131227A1

公开(公告)日：2019-05-02

申请号：US16095916

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Howe Yin LOO ,  Sujit SHARAN ,  Tin Poay CHUAH ,  Ananth PRABHAKUMAR

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L21/48 ,  H01L21/768 ,  H05K1/18

Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

公开(公告)号：US20180145031A1

公开(公告)日：2018-05-24

申请号：US15876080

申请日：2018-01-19

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).