公开(公告)号：US11246218B2

公开(公告)日：2022-02-08

申请号：US15910288

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Ying Wang ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L23/495 ,  H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00 ,  H05K3/06 ,  H01L23/00

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20200373257A1

公开(公告)日：2020-11-26

申请号：US16990782

申请日：2020-08-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US10804188B2

公开(公告)日：2020-10-13

申请号：US16124838

申请日：2018-09-07

Applicant: Intel Corporation

Inventor： Yikang Deng ,  Ying Wang ,  Cheng Xu ,  Chong Zhang ,  Junnan Zhao

IPC: H01L23/498 ,  H01L23/538

Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.

公开(公告)号：US20200312738A1

公开(公告)日：2020-10-01

申请号：US16364540

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Junnan Zhao ,  Cheng Xu ,  Zhimin Wan ,  Yikang Deng ,  Chong Zhang ,  Ying Wang

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/367

Abstract: An integrated circuit assembly may be formed having at least one integrated circuit device electrically attached to an electronic substrate. The integrated circuit assembly may further include at least one heat dissipation device attached to the electronic substrate, wherein the at least one heat dissipation device comprises a phase change material within a containment chamber. The at least one integrated circuit device may be thermally connected to the at least one heat dissipation device with at least one heat transfer structure formed in or on the electronic substrate.

公开(公告)号：US10777514B2

公开(公告)日：2020-09-15

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20200273776A1

公开(公告)日：2020-08-27

申请号：US16287728

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Junnan Zhao ,  Zhimin Wan ,  Ying Wang ,  Yikang Deng ,  Chong Zhang ,  Jiwei Sun ,  Zhenguo Jiang ,  Kyu-Oh Lee

IPC: H01L23/467 ,  H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  H01L23/473 ,  H01L23/31 ,  H01L23/66

Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.

公开(公告)号：US20200168384A1

公开(公告)日：2020-05-28

申请号：US16637006

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Junnan Zhao ,  Ying Wang ,  Cheng Xu ,  Kyu Oh Lee ,  Sheng Li ,  Yikang Deng

IPC: H01F17/00 ,  H01F27/255

Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.

公开(公告)号：US20200027728A1

公开(公告)日：2020-01-23

申请号：US16042203

申请日：2018-07-23

Applicant: Intel Corporation

Inventor： Ying Wang ,  Chong Zhang ,  Meizi Jiao ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments may relate to a semiconductor package that includes a die and a glass core coupled with the die. The glass core may include a cavity with an interconnect structure therein. The interconnect structure may include pads on a first side that are coupled with the die, and pads on a second side opposite the first side. Other embodiments may be described and/or claimed.