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31.发明专利
公开(公告)号：JP2005156888A
公开(公告)日：2005-06-16
申请号：JP2003394672
申请日：2003-11-25
Applicant: Matsushita Electric Works Ltd , 松下電工株式会社
Inventor： KONO KIYOHIKO , HARADA HIROSHI , OKA NAOMASA , NOGE HIROSHI , SUZUKI YUJI , OGIWARA ATSUSHI , JOMI HIROTAKA , USHIYAMA NAOKI
Abstract: PROBLEM TO BE SOLVED: To provide an optical fiber attitude detector and an optical fiber attitude detection method which enhance accuracy and work efficiency of positioning of an optical fiber.
SOLUTION: The optical fiber attitude detector is provided with: an illuminator 4 as a light projection means which irradiates the optical fiber 1b and a fixing member 2 with light from the side opposite from the fixing member 2 with the optical fiber 1b interposed between the illuminator and the fixing member; a camera 3 as an imaging means which images the optical fiber 1b and the fixing member 2 from the side opposite from the fixing member 2 with the optical fiber 1b interposed between the camera and and the fixing member; and a control part 6 which detects attitude of the optical fiber 1b based on light intensity distribution of a side of the optical fiber 1b obtained by performing image processing of an image of the camera 3. Thus, since it is not necessary to check the attitude of the optical fiber 1b by visual observation, the accuracy and the work efficiency of positioning of the optical fiber 1b are enhanced in comparison with the case of checking the attitude of the optical fiber 1b by the visual observation.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供一种提高光纤定位精度和工作效率的光纤姿态检测器和光纤姿态检测方法。 光纤姿态检测器设置有作为光投射装置的照明器4，其将光纤1b和固定部件2从与固定部件2相反的一侧照射光纤1b插入 在所述照明器和所述固定构件之间; 照相机3作为成像装置，其中光纤1b和固定构件之间插入光纤1b，使光纤1b和固定构件2从与固定构件2相反的一侧成像; 以及控制部6，其基于通过对照相机3的图像进行图像处理而获得的光纤1b的一侧的光强度分布来检测光纤1b的姿态。因此，由于不需要检查姿态 通过目视观察，光纤1b的定位精度和工作效率与通过视觉观察检查光纤1b的姿势的情况相比增强。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2003100588A
公开(公告)日：2003-04-04
申请号：JP2001288913
申请日：2001-09-21
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI , OKA NAOMASA , OKUTO TAKASHI
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for forming a resist film with a desired shape without generating resist residual on the surface of a substrate having a slanted face part. SOLUTION: A positive type resist formed on the surface of a substrate is exposed by using a first photo-mask for causing a light beam to be transmitted through a part corresponding to the shape of a resist coating film 21B to be formed. Then, the positive type resist is exposed by using a second photo- mask for causing a light beam to be transmitted through a slanted face part 11C and its outer boundary part 11E.
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33.发明专利
公开(公告)号：JP2003045872A
公开(公告)日：2003-02-14
申请号：JP2001226718
申请日：2001-07-26
Applicant: Matsushita Electric Works Ltd , 松下電工株式会社
Inventor： OKUTO TAKASHI , OKA NAOMASA , OGIWARA ATSUSHI
IPC: H01L21/3205 , H01L23/52
Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure in which incomplete wiring is eliminated without increasing the interval of adjacent lines at a part where the surface of a first semiconductor substrate abuts on the side face of a second semiconductor substrate.
SOLUTION: Wiring trenches 3 are formed on the surface 11 of a first semiconductor substrate 1 in correspondence with a specified wiring shape and a conductive path 4 is provided in the wiring trenches 3. A second semiconductor substrate 2 is bonded onto the surface 11 of the first semiconductor substrate 1 to cover a part of the conduction path 4.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供一种不增加在第一半导体衬底的表面与第二半导体衬底的侧面相邻的部分处的相邻线的间隔的消除不完全布线的布线结构。 解决方案：布线沟槽3形成在第一半导体衬底1的表面11上，与指定的布线形状相对应，并且在布线沟槽3中设置导电路径4.第二半导体衬底2结合到 第一半导体衬底1覆盖导电路径4的一部分。
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34.发明专利
公开(公告)号：JP2002015964A
公开(公告)日：2002-01-18
申请号：JP2000197731
申请日：2000-06-30
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI , OKA NAOMASA
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor wafer product for decoration use, capable of realizing variations of various colors, and to provide a manufacturing/sales system for the semiconductor wafer product which is advanced in cost reduction and in delivery-time shortening. SOLUTION: An electronic file of a drawing patter, which is desired by a customer, is transmitted from a terminal machine 7 of the customer to a printer 9 via a host computer 8 via a telecommunication circuit, and the drawing pattern is printed on an OHP sheet 10. The sheet is brought to a close contact with the surface of a semiconductor wafer 13 that has been covered by photoresist 12, and patterning takes place by irradiation it with a light 14. Namely, by using a commercially available inexpensive OHP film for the photomask, the semiconductor wafer product, on which a drawing pattern is drawn with the contrast among the semiconductor substrate can be manufactured and sold, insulating films and metal films at a low cost and a short delivery time, using conventional OA equipment.
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公开(公告)号：JPH11311578A
公开(公告)日：1999-11-09
申请号：JP11912998
申请日：1998-04-28
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI
Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor pressure sensor base whereby a through hole can be efficiently formed without raising costs. SOLUTION: According to this manufacturing method for a semiconductor pressure sensor base 2 which has a through hole 31 for introducing a pressure to a diaphragm 11 formed at a semiconductor pressure sensor chip 1 and is united to the semiconductor pressure sensor chip 1, a part at one face of a substrate 3 where the through hole 31 is not to be formed is protected by a mask material 6, and a part not protected by the mask material 6 is selectively processed by sand blasting, so that the through hole 31 is formed.
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Patent Agency Ranking
公开(公告)号：JPH10335586A
公开(公告)日：1998-12-18
申请号：JP14171197
申请日：1997-05-30
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OKA NAOMASA , KAMAKURA MASATOMO , OGIWARA ATSUSHI , OKUTO TAKASHI
IPC: H01L27/04 , H01L21/822
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device together with its manufacturing method, wherein a resistance value is adjusted with precision. SOLUTION: A thick silicon oxide film 2 is formed on a single crystal silicon substrate 1, and over it, a polysilicon layer 3a which, being of trapezoid where bottom side is longer, has such impurity distribution as an impurity concentration of phosphorus (P) becomes lower as going deeper under surface is formed. On the surface of polysilicon layer 3a, a silicon oxide film 4 is so formed that a film thickness is minimum near the interface between the polysilicon layer 3a and the silicon oxide film 2, while a polysilicon layer 3b comprising a not or phosphorous (P) is formed from over the silicon oxide film 4 on the polysilicon layer 3a across the silicon oxide film 2. Further, an inter-layer insulation film 5 is formed on such surface side of the single crystal silicon substrate 1 as the polysilicon layers 3a and 3b are formed, and the polysilicon layers 3a and 3b have a part of the silicon oxide film 4 and inter-layer insulation film 5 formed over them are removed, and connected electrically to aluminum wiring electrodes 6a and 6b, respectively.
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公开(公告)号：JPH1012719A
公开(公告)日：1998-01-16
申请号：JP16615496
申请日：1996-06-26
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI
IPC: H01L21/762 , H01L21/304
Abstract: PROBLEM TO BE SOLVED: To provide a dielectric isolation substrate having less warping, and manufacture thereof. SOLUTION: Anisotropic etching is carried out on a single crystal silicon substrate 1 to form a V-shaped groove 1a thereon. Thermal oxidation is carried out to form a silicon oxide film 4 on both sides of the single crystal silicon substrate 1 having the V-shaped groove 1a formed thereon. Subsequently, a filler 8, such as, a SOG film, is formed in such a manner as to fill the V-shaped groove 1a, and a polycrystal silicon film 5 is formed on the filler 8. Finally, the single crystal silicon substrate 1 is polished until a part of the filler 8 is exposed, thus manufacturing a dielectric isolation substrate.
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公开(公告)号：JPH09181167A
公开(公告)日：1997-07-11
申请号：JP34065795
申请日：1995-12-27
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI
IPC: H01L21/762
Abstract: PROBLEM TO BE SOLVED: To reduce warping in an oxydizing process. SOLUTION: Silicon nitride films 7 are formed on the surface and the back of a dielectric isolation substrate 1. Photoresist 8 is spread on the back. The pattern of a single crystal silicon island 4 exposed on the surface is transferred by using an aligner like a contact aligner. By developing, the photoresist 8 of the same pattern as the single crystal silicon island 4 is left on the back of the substrate 1. By using hot phosphoric acid, the silicon nitride film 7 in the part which is not covered with the photoresist 8 is etched, and the photoresist 8 on the back is eliminated by plasma ashing or the like. By covering the back of the substrate 1 with the silicon nitride film 7, the areas of polysilicon layers 2a, 2b exposed on the surface and the back of the substrate 1 which are oxidized in the oxidizing process in a diffusion process are made equal. The expansion of the polysilicon layers 2a, 2b on the surface and the back of the substrate 1 is balanced, and generation of warping of the dielectric isolation substrate 1 can be prevented.
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公开(公告)号：JPH09172065A
公开(公告)日：1997-06-30
申请号：JP33300795
申请日：1995-12-21
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI
IPC: H01L21/762 , H01L23/14
Abstract: PROBLEM TO BE SOLVED: To provide a dielectric isolating substrate whose warp is little. SOLUTION: A dielectric isolating substrate 1 is composed of a polysilicon layer 2a deposited by a vapor growth (CVD) method, and a polysilicon later 2b whose crystal grain diameter is smaller than that of the polysilicon layer 2a. In this case on the surface of the polysilicon layer 2b, single crystal silicon islands 4, made out of single crystal silicon and insulated individually electrically, whose sides and bottoms are covered with silicon oxide films 3 are arranged by a desired pattern. Accordingly, crystal grain boundaries become fewer, sine the grains of the polysilicon layer 2a are made larger than those of the polysilicon layer 2b. it becomes possible to prevent the shrinkage of the polysilicon layer 2a caused by the mutual uniting of grains, and the expansion of the polysilicon layer 2a caused by the diffusion of oxygen in an oxidizing process, and the warpage of the dielectric isolating substrate 1 can be lessened.
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公开(公告)号：JPH0946204A
公开(公告)日：1997-02-14
申请号：JP19231295
申请日：1995-07-27
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： MIYAJIMA HISAKAZU , YAMAGUCHI SHUICHIRO , OGIWARA ATSUSHI , SUGIURA YOSHIYUKI
IPC: H03K17/78
Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive product with a small area by connecting the drain of second MOSFET to the gate of output MOSFET and the gate of second MOSFET to a source through a resistance element. SOLUTION: When a signal is applied between terminals 7A and 7B, a diode 1 outputs a signal. An array 2 receiving the signal outputs electromotive force and current flows through second MOSFET 9, the resistance element 10, first MOSFET 6 and a high resistance element 4. Voltage is generated on the both ends of the high resistance element 4. Output MOSFET 3 moderately shifts to an on-state. Charge accumulated in output MOSFET 3 is discharged with signal interruption between the terminals. This, output MOSFET 3 moderately shifts to an off-state.
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