公开(公告)号：JPH10335466A

公开(公告)日：1998-12-18

申请号：JP13691897

申请日：1997-05-27

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA ,  KAMAKURA MASATOMO ,  OGIWARA ATSUSHI ,  OKUTO TAKASHI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its fabrication method which can adjust the resistance value with high precision. SOLUTION: An n+type impurity region 2 is formed in a single-crystal silicon substrate 1 such that the region 2 encloses a V-shaped trench portion 1a formed on one main surface of the single-crystal silicon substrate 1. A phosphorus (P) rich polycrystal silicon layer 4 is formed at the surface side on which the trench portion 1a of the polycrystal substrate 1 is formed by way of a silicon oxide film 3 having a thin film thickness. The silicon oxide film 3 is formed in such a manner that the film thickness becomes thinnest at the bottom portion of the trench portion 1a and the polycrystal silicon layer 4 is disposed at the portion where the trench portion 1a is formed. An interlayer insulation film 5 is formed on the silicon oxide film 3 and the polycrystal silicon layer 4. The silicon oxide film 3 and the interlayer insulation film 5 which are formed on the upper portion of the n+type impurity region 2 and the polycrystal silicon layer 4 have respective parts thereof removed so as to connect the n+type impurity region 2 and the polycrystal silicon layer 4 with aluminum wiring electrodes 6a, 6b.

公开(公告)号：JPH10335447A

公开(公告)日：1998-12-18

申请号：JP14171797

申请日：1997-05-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI ,  OKA NAOMASA ,  OKUTO TAKASHI ,  KAMAKURA MASATOMO

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/76 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a dielectric isolation substrate which can prevent generation of a void at a tip end of a V-shaped groove. SOLUTION: A polysilicon layer 5a is formed as deposited on a side of a single crystal silicon substrate 1 having a groove 1a made therein by a CD process using trichlorosilane and hydrogen gases as source gases. At this time, a temperature within a reactor where the polysilicon layer 5a is to be deposited is previously set at less than 1150 deg.C. Next, the temperature within the reactor is set at 1150 deg.C or more without causing any change in the flow rates of the source gases, to thereby form an upper polysilicon layer 5b through deposition. Finally, the substrate is polished from a side of the substrate not provided with the layer 5b until the layer 5a buried in the groove 1a is exposed, to thereby silicon single crystal islands 6 of the substrate 1 covered on its bottom and side faces with a silicon oxide film 4. That is, the layer 5b is polished down to a predetermined thickness.

公开(公告)号：JPH10335586A

公开(公告)日：1998-12-18

申请号：JP14171197

申请日：1997-05-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA ,  KAMAKURA MASATOMO ,  OGIWARA ATSUSHI ,  OKUTO TAKASHI

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device together with its manufacturing method, wherein a resistance value is adjusted with precision. SOLUTION: A thick silicon oxide film 2 is formed on a single crystal silicon substrate 1, and over it, a polysilicon layer 3a which, being of trapezoid where bottom side is longer, has such impurity distribution as an impurity concentration of phosphorus (P) becomes lower as going deeper under surface is formed. On the surface of polysilicon layer 3a, a silicon oxide film 4 is so formed that a film thickness is minimum near the interface between the polysilicon layer 3a and the silicon oxide film 2, while a polysilicon layer 3b comprising a not or phosphorous (P) is formed from over the silicon oxide film 4 on the polysilicon layer 3a across the silicon oxide film 2. Further, an inter-layer insulation film 5 is formed on such surface side of the single crystal silicon substrate 1 as the polysilicon layers 3a and 3b are formed, and the polysilicon layers 3a and 3b have a part of the silicon oxide film 4 and inter-layer insulation film 5 formed over them are removed, and connected electrically to aluminum wiring electrodes 6a and 6b, respectively.

公开(公告)号：JPH11242050A

公开(公告)日：1999-09-07

申请号：JP6060998

申请日：1998-02-24

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： NAKAMURA TAKURO ,  YOSHIDA HITOSHI ,  ISHIDA TAKUO ,  TOMONARI SHIGEAKI ,  KAMAKURA MASATOMO ,  OKA NAOMASA

IPC: G01L5/16 ,  G01P15/12 ,  G01P15/18

Abstract: PROBLEM TO BE SOLVED: To provide a three-axis acceleration sensor with improved sensitivity by narrowing the essential total width of a beam for constituting a flexible part. SOLUTION: A flexible part 2 is constituted of two parallel beams 21 and another beam 22 that is formed for connecting base parts at the side of a fixing part, and the width of the essential flexible part 2 is narrowed. A piezo resistor 23 or 24 for x or y axis is formed at the connection site with a connection part 3 of each beam 21, and a piezo resistor 25 for z axis is formed at another beam 22.

公开(公告)号：JPH10335457A

公开(公告)日：1998-12-18

申请号：JP14171297

申请日：1997-05-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA ,  KAMAKURA MASATOMO ,  OGIWARA ATSUSHI ,  OKUTO TAKASHI

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can adjust its resistive value accurately, and a method for manufacturing the semiconductor device. SOLUTION: Formed on a single crystal silicon substrate 1 is a thick silicon oxide film 2, on which is formed a polysilicon layer 3a. The layer 3a has such an impurity distribution that a phosphorus (P) concentration is increased as a depth from the film 2 increases, and has a trapezoidal shape having a shorter lower bottom side. Formed on the layer 3a is a silicon oxide film 4 so as to have a minimum thickness at an upper bottom end of the layer 3a, on which is further formed a polysilicon layer 3b so that an amount of phosphorus (P) is increased as it goes from the film 4 on the layer 3a upto the surface of the film 2. And an interlayer insulating film 5 is formed on a side of the substrate 2 provided with the layers 3a and 3b. The films 4 and 5 formed on the layers 3 and 3b are partially removed to be electrically connected to respective aluminum wiring electrodes 6a and 6b.

公开(公告)号：JPH10335446A

公开(公告)日：1998-12-18

申请号：JP14171697

申请日：1997-05-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI ,  OKA NAOMASA ,  OKUTO TAKASHI ,  KAMAKURA MASATOMO

IPC: H01L21/762 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a dielectric isolation substrate which can prevent generation of a void at a tip end of a V-shaped groove. SOLUTION: A polysilicon layer 5a is formed as deposited on a side of a single crystal silicon substrate 1 having a groove 1a made therein by a CD process using trichlorosilane and hydrogen gases as source gases. At this time, flow rates of the source gases, especially the flow rate of the trichlorosilane gas is adjusted so that a deposition rate of the polysilicon layer 5a is 2 μm/min. or less. Next, the flow rates of the source gases, especially, the flow rate of the trichlorosilane gas is increased to set the deposition rate at 2 μm/min. or more, under the condition of which an upper polysilicon layer 5b is deposited.