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    AN INVERTER CIRCUIT HAVING A FEEDBACK SWITCH AND METHODS CORRESPONDING THERETO
    31.
    发明申请
    AN INVERTER CIRCUIT HAVING A FEEDBACK SWITCH AND METHODS CORRESPONDING THERETO 审中-公开
    具有反馈开关的逆变器电路和与之相关的方法

    公开(公告)号：WO2007050403A2

    公开(公告)日：2007-05-03

    申请号：PCT/US2006040791

    申请日：2006-10-20

    Applicant: MOTOROLA INC ,  BRAZIS PAUL W ,  GAMOTA DANIEL R ,  TSUI KIN P ,  SZCZECH JOHN B ,  ZHANG JIE

    Inventor： BRAZIS PAUL W ,  GAMOTA DANIEL R ,  TSUI KIN P ,  SZCZECH JOHN B ,  ZHANG JIE

    IPC: H03K19/094

    CPC classification number: H03K19/01721 ,  H03K19/09441

    Abstract: An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401). In a preferred approach the feedback switch is itself also operably coupled to the voltage bias input and the output and preferably serves, when the drive transistor is switched "off", to responsively couple the voltage bias input to the drive transistor in such a way as to cause a gate terminal of the drive transistor to have its polarity relative to a source terminal of the drive transistor reversed and hence permit the inverter circuit to operate across a substantially full potential operating range of the drive transistor.

    Abstract translation: 一种具有可操作地耦合到电压偏置输入（101）的驱动晶体管（102）的逆变器电路（500），并且其中驱动晶体管通过打开和关闭输出（105）和地（ 104））进一步可操作地耦合到反馈开关（401）。 在优选的方法中，反馈开关本身也可操作地耦合到电压偏置输入端和输出端，并且优选地在驱动晶体管被切换为“断开”时，将电压偏置输入端以这样的方式响应地耦合到驱动晶体管： 以使驱动晶体管的栅极端子相对于驱动晶体管的源极端子的极性相反，从而允许逆变器电路在驱动晶体管的基本上全部的电位工作范围内工作。

    SEMICONDUCTOR DEVICE HAVING SILANE TREATED INTERFACE
    32.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SILANE TREATED INTERFACE 审中-公开
    具有硅烷处理界面的半导体器件

    公开(公告)号：WO2010019357A3

    公开(公告)日：2011-03-03

    申请号：PCT/US2009051330

    申请日：2009-07-22

    Applicant: MOTOROLA INC ,  ZHANG JIE ,  GAMOTA DANIEL R ,  JIANG LIN

    Inventor： ZHANG JIE ,  GAMOTA DANIEL R ,  JIANG LIN

    IPC: H01L51/10 ,  H01L51/40

    CPC classification number: H01L51/0022 ,  H01L51/0004 ,  H01L51/0529 ,  H01L51/0545 ,  H01L51/102

    Abstract: A semiconductor device made on a polymer substrate (10) using graphic arts printing technology uses a printable organic semiconductor. An electrode (14) is situated on the substrate (10), and a dielectric layer (20) is situated over the electrode (14). Another electrode(s) (25, 26) is situated on the dielectric layer (20). The exposed surfaces of the dielectric (20) and the top electrode (25, 26) are treated with a reactive silane to alter the surface of the electrode (25, 26) and the dielectric (20) sufficiently to allow an overlying organic semiconductor layer to have good adhesion to both the electrode (25, 26) and the dielectric (20). In various embodiments, the electrodes (14, 25, 26) may be printed, and the dielectric layer (20) may also be printed.

    Abstract translation: 使用图形印刷技术在聚合物基板（10）上制造的半导体器件使用可印刷的有机半导体。 电极（14）位于基板（10）上，电介质层（20）位于电极（14）上方。 另一个电极（25,26）位于电介质层（20）上。 电介质（20）和顶部电极（25,26）的暴露表面用反应性硅烷处理以充分改变电极（25,26）和电介质（20）的表面，以允许上覆的有机半导体层 以对电极（25,26）和电介质（20）两者具有良好的附着力。 在各种实施例中，可以印刷电极（14,25,26），并且还可以印刷电介质层（20）。

    PIEZOELECTRIC STRUCTURES HAVING CONTROLLABLE OPTICAL SURFACES
    38.
    发明申请
    PIEZOELECTRIC STRUCTURES HAVING CONTROLLABLE OPTICAL SURFACES 审中-公开
    具有可控光学表面的压电结构

    公开(公告)号：WO03005100A3

    公开(公告)日：2003-10-02

    申请号：PCT/US0212913

    申请日：2002-04-24

    Applicant: MOTOROLA INC

    Inventor： KLOSOWIAK TOMASZ L ,  GAMOTA DANIEL R ,  LEMPKOWSKI ROBERT B

    IPC: G02B26/08 ,  H01L41/22 ,  H01L27/20

    CPC classification number: G02B26/0858 ,  H01L41/319

    Abstract: High quality epitaxial layers of monocrystalline materials (126) can be grown overlying monocrystalline substrates (102) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (104) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (108) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Further, various shaped piezoelectric structures (132) having optical surfaces (134) may be disposed on the overlying monocrystalline layer for optical switching and controlled manipulation of light signals.

    Abstract translation: 通过形成用于生长单晶层的顺应性衬底，可以将单晶材料（126）的高质量外延层生长在覆盖单晶衬底（102），例如大硅晶片上。 容纳缓冲层（104）包括通过氧化硅的非晶界面层（108）与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 此外，具有光学表面（134）的各种成形的压电结构（132）可以设置在上覆单晶层上，用于光信号的光学切换和受控操纵。

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