公开(公告)号：US20220129204A1

公开(公告)日：2022-04-28

申请号：US17516009

申请日：2021-11-01

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Peter Feeley ,  Qisong Lin

IPC: G06F3/06

Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.

公开(公告)号：US11282564B1

公开(公告)日：2022-03-22

申请号：US17094970

申请日：2020-11-11

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Ashutosh Malshe ,  Gianni S. Alsasua

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/409 ,  G11C29/44

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including identifying, among a first plurality of wordlines of a set of pages of the memory device, at least one wordline having a current value of a data state metric satisfying a first condition; determining new values of the data state metric of a second plurality of wordlines of the set of pages, wherein the at least one wordline is excluded from the second plurality of wordlines; and responsive to determining that the new values of the data state metric of one or more wordlines of the second plurality of wordlines satisfy a second condition, performing a media management operation with respect to the one or more wordlines.

公开(公告)号：US20220083408A1

公开(公告)日：2022-03-17

申请号：US17531960

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Harish R. Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F11/07 ,  G11C29/00

Abstract: A method includes obtaining a first operation execution time corresponding to an operation performed on a page of a first data unit of a memory device, determining whether the first operation execution time satisfies a condition that is based on a second operation execution time, wherein the second operation execution time is indicative of lack of defect in at least a second data unit of the memory device, and responsive to determining that the first operation execution time satisfies the condition that is based on the second operation execution time, initiating a defect scan operation of at least a subset of pages of the first data unit.

公开(公告)号：US20220076765A1

公开(公告)日：2022-03-10

申请号：US17014583

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Larry J. Koudele

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/32 ,  G11C7/04

Abstract: An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.

公开(公告)号：US11270772B1

公开(公告)日：2022-03-08

申请号：US17008225

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Michael Sheperek ,  Larry J. Koudele ,  Shane Nowell

IPC: G11C16/10 ,  G06F12/06 ,  G11C16/08

Abstract: One or more blocks at the memory device are programed. The one or more blocks are associated with a block family and with one or more dice of a die group. A voltage offset bin associated with the die group and the block family is determined based on a subset of dice of the die group. Metadata associated with the memory device is appended to include a record associating the die group and the block family with the voltage offset bin.

公开(公告)号：US20220066678A1

公开(公告)日：2022-03-03

申请号：US17002374

申请日：2020-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R. Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  G06F11/10 ,  H03M7/30

Abstract: parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.

公开(公告)号：US20210311649A1

公开(公告)日：2021-10-07

申请号：US17350866

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Peter Feeley ,  Qisong Lin

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.

公开(公告)号：US11126495B2

公开(公告)日：2021-09-21

申请号：US15914858

申请日：2018-03-07

Applicant: Micron Technology, Inc.

Inventor： Renato Padilla, Jr. ,  Gary F. Besinga ,  Harish Singidi ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam

IPC: G06F11/07 ,  G06F11/30

Abstract: A system configured to determine that a trigger condition has occurred that is related to an operation performed on a memory device of the system. Responsive to determining that the trigger condition has occurred, reordering error handling mechanisms of an error handling sequence based upon an error handling mechanism performance metric. Each error handling mechanism specifies operations to be performed to recover an error in the operation on the memory device.

公开(公告)号：US11106532B1

公开(公告)日：2021-08-31

申请号：US16862446

申请日：2020-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F12/0882 ,  G06F11/30 ,  G06F12/02

Abstract: A processing device, operatively coupled with the memory device, is configured to perform a first program erase cycle (PEC) on a data unit of a memory device, wherein performing the first PEC comprises scanning a first set of pages of a plurality of pages of the data unit to determine a first error rate. The processing device also determines a first pattern of error rate change for the data unit based on the first error rate and a second error rate. The processing device then compares the first pattern of error rate change for the data unit with a predetermined pattern of error rate that is indicative of a defect. Responsive to determining that the first pattern of error rate change corresponds to the predetermined pattern of error rate change, the processing device performs an action pertaining to defect remediation with respect to the data unit.

公开(公告)号：US10956053B2

公开(公告)日：2021-03-23

申请号：US16209007

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Harish R. Singidi

IPC: G06F3/00 ,  G06F3/06 ,  G06F16/23

Abstract: A data integrity check is performed on a data block of the memory component to obtain a reliability statistic for each of a set of sampled memory cells in the data block. A distribution statistic is determined based on the reliability statistic for each of the set of sampled memory cells. A subset of the data block is identified to be relocated to another data block of the memory component based on the distribution statistic. Data of the subset of the data block is relocated to the other data block.