公开(公告)号：US12062656B2

公开(公告)日：2024-08-13

申请号：US17514507

申请日：2021-10-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/00 ,  H01L21/761 ,  H01L23/528 ,  H01L27/088 ,  H01L23/00

CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L23/528 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

公开(公告)号：US12027575B2

公开(公告)日：2024-07-02

申请号：US18333507

申请日：2023-06-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L23/52 ,  H01G4/30 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L23/5223

Abstract: A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

公开(公告)号：US11876072B2

公开(公告)日：2024-01-16

申请号：US17465328

申请日：2021-09-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Zhong Li ,  Yi-Ting Shih ,  Chien-Chung Wang ,  Hsih-Yang Chiu

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/48824 ,  H01L2224/85031 ,  H01L2224/85359

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

公开(公告)号：US11776924B2

公开(公告)日：2023-10-03

申请号：US17546275

申请日：2021-12-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/76895 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/039 ,  H01L2224/05547 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

公开(公告)号：US11676886B2

公开(公告)日：2023-06-13

申请号：US17324101

申请日：2021-05-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung Wang ,  Hsih-Yang Chiu

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2924/1533

Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.

公开(公告)号：US11676857B2

公开(公告)日：2023-06-13

申请号：US17511211

申请日：2021-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/321

CPC classification number: H01L21/76829 ,  H01L21/32115 ,  H01L21/76814 ,  H01L21/823821

Abstract: A method includes providing a first wafer including a first substrate, a first dielectric layer disposed over the first substrate and a first component formed within the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer disposed over the second substrate, and a second component formed within the second dielectric layer; removing a first portion of the first dielectric layer to form a first recess; removing a second portion of the second dielectric layer to form a second recess; disposing the second wafer over the first wafer to bond the first dielectric layer to the second dielectric layer; removing a third portion of the second substrate and the second dielectric layer to form a third recess coupled to the second recess; and disposing a conductive material to fill the first recess, the second recess and the third recess to form a conductive structure.

公开(公告)号：US11307249B1

公开(公告)日：2022-04-19

申请号：US17136777

申请日：2020-12-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Wei-Zhong Li ,  Hsih-Yang Chiu

IPC: G01R31/28 ,  G01R27/08 ,  G01R31/30

Abstract: The present application discloses a method for characterizing a resistance state of a programmable element of an integrated circuit. The method includes the steps of setting a first programming voltage of a first polarity to program the programmable element of the integrated circuit, setting a first read voltage of the first polarity to the integrated circuit at a first temperature to obtain a first read current, and a first resistance is derived from the first read current, setting the first read voltage of the first polarity to the integrated circuit at a second temperature to obtain a second read current, the second temperature is at least 50° C. higher than the first temperature, and a second resistance is derived from the second read current, and comparing the first resistance and the second resistance to characterize the resistance state of the programmable element.

公开(公告)号：US11257694B2

公开(公告)日：2022-02-22

申请号：US16781377

申请日：2020-02-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/67 ,  H01L23/528 ,  H01L23/00

Abstract: The present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device and a mothed of method of manufacturing a semiconductor device assembly. The semiconductor device includes a substrate, a bonding dielectric disposed on the substrate, a first conductive feature disposed in the bonding dielectric, an air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric, and a second conductive feature including a base disposed in the bonding dielectric and a protrusion stacked on the base.

公开(公告)号：US11171087B1

公开(公告)日：2021-11-09

申请号：US16868304

申请日：2020-05-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/525 ,  H01L27/085 ,  H01L27/112

Abstract: The present disclosure provides a semiconductor structure employing an antifuse structure and a controlling method of the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a transistor and an antifuse structure. The transistor is disposed on the semiconductor substrate. The antifuse structure is disposed on the semiconductor substrate and adjacent to the transistor. The antifuse structure includes a first conductive portion, a fusible portion and a second conductive portion. The first conductive portion is disposed in the semiconductor substrate. The fusible portion is disposed on the first conductive portion. The second conductive portion is disposed on the fusible portion. The antifuse structure encloses the transistor in a top view.

公开(公告)号：US11031462B1

公开(公告)日：2021-06-08

申请号：US16724393

申请日：2019-12-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L29/06 ,  H01L23/48

Abstract: A semiconductor structure includes a semiconductor wafer having a topside and a backside. The wafer includes a first semiconductor well of a first conductive type, a second semiconductor well of a second conductive type different from the first conductive type, a plurality of first semiconductor doped regions of the first conductive type and a plurality of first through silicon vias (TSVs) filled with conductive material. The first semiconductor well is formed within the second semiconductor well and exposed to the topside. The semiconductor device and the first semiconductor doped regions are formed within the first semiconductor well, and the first semiconductor doped regions surround the semiconductor device. Each first TSV extends into a corresponding one of the first semiconductor doped regions from the backside through the first and second semiconductor wells and is connected to a DC voltage or a ground potential from the backside.