公开(公告)号：AU6027099A

公开(公告)日：2000-03-21

申请号：AU6027099

申请日：1999-09-02

Applicant: QUALCOMM INC

Inventor： LEE WAY-SHING

IPC: G06F12/14 ,  G06F11/00 ,  G06F21/02 ,  H04M1/00 ,  H04M1/60 ,  H04M11/00 ,  H04Q3/545 ,  H04M1/725

Abstract: A hands free telephone system includes a telephone having audio circuits for processing an audio signal and a telephone audio connector for transmitting the audio signal between the audio circuits and the telephone audio connector. A telephone holder has a holder program for instructing the telephone holder to perform telephone functions in accordance with the stored program. The telephone holder has a holder audio connector for mechanically mating with the telephone audio connector and transmitting the audio signal between the telephone audio connector and the programmable holder. A programming device includes circuitry for storing and transmitting the holder program and the programming device has a programming connector for mechanically mating with the holder audio connector and transmitting the holder program between the programming device and the telephone holder by way of the mated programming connector and the holder audio connector, whereby the holder audio connector is adapted to transmit both the audio signal and the holder stored program. The telephone audio connector can be disposed upon the telephone holder.

公开(公告)号：WO2005089116A3

公开(公告)日：2007-01-25

申请号：PCT/US2005006907

申请日：2005-03-02

Applicant: QUALCOMM INC ,  SIH GILBERT C ,  HSU DE D ,  LEE WAY-SHING ,  CHEN XUFENG

Inventor： SIH GILBERT C ,  HSU DE D ,  LEE WAY-SHING ,  CHEN XUFENG

IPC: G06F9/30

CPC classification number: G06F9/30014 ,  G06F9/30032 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3893

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Abstract translation: 描述了具有改进性能的DSP架构。 在示例性架构中，DSP包括两个MAC单元和两个ALU，其中一个ALU替换两个MAC单元之一的加法器。 该DSP可以被配置为以双MAC /单ALU配置，单MAC /双ALU配置或双MAC /双ALU配置来操作。 这种灵活性允许DSP处理各种类型的信号处理操作，并提高可用硬件的利用率。 DSP架构还包括流水线寄存器，其分解关键路径，并允许以更高的时钟速度进行操作以获得更高的吞吐量。

公开(公告)号：WO0197400A3

公开(公告)日：2002-03-28

申请号：PCT/US0119403

申请日：2001-06-14

Applicant: QUALCOMM INC

Inventor： ROWITCH DOUGLAS NEAL ,  LEE WAY-SHING ,  EKVETCHAVIT THUNYACHATE

IPC: H04B1/7075 ,  H04B1/708 ,  H04B1/709 ,  H04B7/06 ,  H04J13/00 ,  H04B1/707

CPC classification number: H04B1/70751 ,  H04B1/70752 ,  H04B1/708 ,  H04B1/709 ,  H04B7/0613 ,  H04J13/004

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered "half-symbols" and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the lenght (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodualted symbols. One or more correlators can be assigned to process one or more instances of each transmiteed signal. The pilot estimates used within each assigned correlator to demodulate the decovered half-symbols are generated based on the signal instance being prcessed by that correlator.

Abstract translation: 用于在无线通信系统中处理接收到的信号的解调器架构。 解调器包括耦合到组合器的多个相关器。 每个相关器通常以相应的解扩序列接收和解扩输入采样（其从接收信号产生），以提供解扩样本。 每个相关器然后解码解扩样本以提供去除的“半符号”，并且用导频估计进一步解调已解除的半符号以产生相关符号。 使用具有用于覆盖所发送的信号中的数据符号的沃尔什符号的长度（2T）的一半的长度（T）的沃尔什符号执行解复用。 组合器选择性地组合来自所分配的相关器的相关符号以提供解调符号。 可以分配一个或多个相关器来处理每个透过信号的一个或多个实例。 在每个分配的相关器内使用的导频估计是基于被该相关器加权的信号实例来生成的。

公开(公告)号：WO0163379A3

公开(公告)日：2003-10-16

申请号：PCT/US0105871

申请日：2001-02-23

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  KUMAR HEMANT ,  LEE WAY-SHING

IPC: G06F7/00 ,  G06F7/48 ,  G06F7/544 ,  G06F9/302 ,  G06F9/38 ,  G06F15/78 ,  G06F9/30

CPC classification number: G06F9/3877 ,  G06F7/4812 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/3893 ,  G06F15/7817

Abstract: The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.

Abstract translation: 本发明是一种数字信号处理器架构，其被设计为加速频繁使用的信号处理计算，例如FIR滤波器，相关性，FFT和DFT。 该架构使用耦合的双MAC架构（MAC1）（MAC2），并以独特的方式将双MAC协处理器（MAC3）（MAC4）附加到其上，以实现处理能力的显着增加。

公开(公告)号：EP1763739A4

公开(公告)日：2008-07-16

申请号：EP05724448

申请日：2005-03-02

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  HSU DE D ,  LEE WAY-SHING ,  CHEN XUFENG

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F9/30014 ,  G06F9/30032 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3893

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.