公开(公告)号：JP2010282637A

公开(公告)日：2010-12-16

申请号：JP2010157075

申请日：2010-07-09

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F13/16 ,  G06F15/78

CPC classification number: G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

Abstract: PROBLEM TO BE SOLVED: To provide a digital signal processor which enhances performance and availability. SOLUTION: A DSP includes a set of three data buses over which data may be exchanged with a register bank 120 and three data memories 102, 103 and 104. The register bank 120 may be used that includes registers accessible by at least two processing units 128 and 130. An instruction fetch unit 156 may include that receives instructions of variable length stored in an instruction memory 152. The instruction memory 152 may be separated from the set of three data memories 102, 103 and 104. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提高性能和可用性的数字信号处理器。 解决方案：DSP包括一组三条数据总线，数据可以通过该组三个数据总线与寄存器组120和三个数据存储器102,103和104进行交换。可以使用寄存器组120，其包括可由至少两个 处理单元128和130.指令提取单元156可以包括接收存储在指令存储器152中的可变长度的指令。指令存储器152可以与三组数据存储器102,103和104分离。 ：（C）2011，JPO＆INPIT

公开(公告)号：DE60034551T2

公开(公告)日：2007-12-27

申请号：DE60034551

申请日：2000-02-04

Applicant: QUALCOMM INC

Inventor： CHANG CHIENCHUNG ,  LEE WAY-SHING ,  OPALSKY ROBERT ,  PAN GEORGE ,  CHINNASWAMI KARTHICK ,  HUANG HANCHI DAVID ,  DEN BESTE STEVEN C

IPC: H04B1/38 ,  H04B1/40 ,  H04B20060101 ,  H04B7/212 ,  H04B14/04 ,  H04J3/00 ,  H04L7/00 ,  H04L7/04 ,  H04L12/64 ,  H04M20060101 ,  H04M1/60 ,  H04M1/725 ,  H04Q20060101 ,  H04Q7/32

Abstract: A method and apparatus for communicating both voice and control data between a communication device (such as a cellular phone) and an external accessory (such as a hands-free kit) over a data bus. The method includes formatting a sequence of bits into a repeating sequence of first time slots and second time slots, transmitting the voice data in the first time slot, and transmitting the control data in the second time slot. Notably, a first bit of each of the second time slots comprises a clock bit that alternates between a high value and a low value (e.g. a "1' or a "0') as between consecutive second time slots.

公开(公告)号：AR033902A1

公开(公告)日：2004-01-07

申请号：ARP020101864

申请日：2002-05-20

Applicant: QUALCOMM INC

Inventor： CHALLA RAGHU ,  LEE WAY-SHING ,  SIH GIL ,  ABRISHAMKAR FARROKH ,  GLAZKO SERGUEI ,  PATRICK CHRISTOPHER ,  FEVRIER IAN

IPC: H04B7/26 ,  H04B1/00

Abstract: Un dispositivo inalámbrico de espectro ancho 100 que puede incluir un receptor 110, un buscador 128, un controlador de búsqueda 130 y otras características. El controlador de búsqueda 130 genera de manera selectiva senales de control para controlar al buscador 128, el cual busca una senal de espectro ancho. En una forma de realización, la arquitectura del buscador 128 es configurable de manera dinámica por el controlador de búsqueda 130 para buscar de manera selectiva canales múltiples que utilizan recipientes de frecuencia múltiple para la senal

公开(公告)号：HK1055180A1

公开(公告)日：2003-12-24

申请号：HK03107435

申请日：2003-10-15

Applicant: QUALCOMM INC

Inventor： ROWITCH DOUGLAS NEAL ,  LEE WAY-SHING ,  EKVETCHAVIT THUNYACHATE

IPC: H04B1/7075 ,  H04B1/708 ,  H04B1/709 ,  H04B7/06 ,  H04J13/00 ,  H04B

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal. The pilot estimates used within each assigned correlator to demodulate the decovered half-symbols are generated based on the signal instance being processed by that correlator.

公开(公告)号：AU3984601A

公开(公告)日：2001-09-03

申请号：AU3984601

申请日：2001-02-23

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  KUMAR HEMANT ,  LEE WAY-SHING

IPC: G06F7/00 ,  G06F7/48 ,  G06F7/544 ,  G06F9/302 ,  G06F9/38 ,  G06F15/78

Abstract: The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.

公开(公告)号：DE60034551D1

公开(公告)日：2007-06-06

申请号：DE60034551

申请日：2000-02-04

Applicant: QUALCOMM INC

Inventor： CHANG CHIENCHUNG ,  LEE WAY-SHING ,  OPALSKY ROBERT ,  PAN GEORGE ,  CHINNASWAMI KARTHICK ,  HUANG HANCHI DAVID ,  DEN BESTE STEVEN C

IPC: H04B1/38 ,  H04B1/40 ,  H04B20060101 ,  H04B7/212 ,  H04B14/04 ,  H04J3/00 ,  H04L7/00 ,  H04L7/04 ,  H04L12/64 ,  H04M20060101 ,  H04M1/60 ,  H04M1/725 ,  H04Q20060101 ,  H04Q7/32

Abstract: A method and apparatus for communicating both voice and control data between a communication device (such as a cellular phone) and an external accessory (such as a hands-free kit) over a data bus. The method includes formatting a sequence of bits into a repeating sequence of first time slots and second time slots, transmitting the voice data in the first time slot, and transmitting the control data in the second time slot. Notably, a first bit of each of the second time slots comprises a clock bit that alternates between a high value and a low value (e.g. a "1' or a "0') as between consecutive second time slots.

公开(公告)号：AT360923T

公开(公告)日：2007-05-15

申请号：AT00907156

申请日：2000-02-04

Applicant: QUALCOMM INC

Inventor： CHANG CHIENCHUNG ,  LEE WAY-SHING ,  OPALSKY ROBERT ,  PAN GEORGE ,  CHINNASWAMI KARTHICK ,  HUANG HANCHI DAVID ,  DEN BESTE STEVEN C

IPC: H04B1/40 ,  H04B20060101 ,  H04B1/38 ,  H04B7/212 ,  H04B14/04 ,  H04J3/00 ,  H04L7/00 ,  H04L7/04 ,  H04L12/64 ,  H04M20060101 ,  H04M1/60 ,  H04M1/725 ,  H04Q20060101 ,  H04Q7/32

Abstract: A method and apparatus for communicating both voice and control data between a communication device (such as a cellular phone) and an external accessory (such as a hands-free kit) over a data bus. The method includes formatting a sequence of bits into a repeating sequence of first time slots and second time slots, transmitting the voice data in the first time slot, and transmitting the control data in the second time slot. Notably, a first bit of each of the second time slots comprises a clock bit that alternates between a high value and a low value (e.g. a "1' or a "0') as between consecutive second time slots.

公开(公告)号：HK1094608A1

公开(公告)日：2007-04-04

申请号：HK07101408

申请日：2001-09-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP I ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：CA2558367A1

公开(公告)日：2005-09-29

申请号：CA2558367

申请日：2005-03-02

Applicant: QUALCOMM INC

Inventor： CHEN XUFENG ,  SIH GILBERT C ,  LEE WAY-SHING ,  HSU DE D

IPC: G06F7/48 ,  G06F7/57 ,  G06F9/30

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

公开(公告)号：CA2324219C

公开(公告)日：2011-05-10

申请号：CA2324219

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A ,  KANG INYUP

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).