-
公开(公告)号：JP2010193489A
公开(公告)日：2010-09-02
申请号：JP2010085217
申请日：2010-04-01
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture providing a signal gain and DC offset correction. SOLUTION: The direct downconversion receiver architecture includes: a DC loop to remove DC offset from signal components; a digital variable gain amplifier (DVGA) to provide a range of gains; an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry; and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop is selected based on the operating mode of the DC loop, since these two loops interact with each other. The duration of time the DC loop is operated in an acquisition mode is selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种提供信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收机架构包括：DC信号消除DC偏移的DC环路; 数字可变增益放大器（DVGA）提供一系列增益; 自动增益控制（AGC）回路，为DVGA和RF /模拟电路提供增益控制; 以及串行总线接口（SBI）单元，通过串行总线提供对RF /模拟电路的控制。 基于DC环路的工作模式选择VGA环路的工作模式，因为这两个环路相互交互。 在采集模式下，DC环路工作的持续时间被选择为与采集模式中的DC环路带宽成反比。 版权所有（C）2010，JPO＆INPIT
-
公开(公告)号：JP2010213310A
公开(公告)日：2010-09-24
申请号：JP2010094023
申请日：2010-04-15
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide an architecture of a direct down conversion receiver capable of providing required signal gain and DC offset correction. SOLUTION: The architecture has a DC loop for removing DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing a gain control relating to the DVGA and an RF/analog circuit, and a serial bus interface (SBI) unit for providing control to the RF/analog circuit via a serial bus. Since these two loops perform mutual interaction with each other in design and disposition of the DVGA, an operation mode of the VGA loop is selected based on an operation mode of the DC loop. Within a time period while the DC loop is operating by a capturing mode, selection is made so as to be operated in inverse proportion to a bandwidth of the DC loop in the capturing mode. The control relating to some or all of RF/analog circuits is provided via the serial bus. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机的架构。 解决方案：该架构具有用于从信号分量中去除DC偏移的直流回路，用于提供增益范围的数字可变增益放大器（DVGA），用于执行与增益范围相关的增益控制的自动增益控制（AGC） DVGA和RF /模拟电路以及串行总线接口（SBI）单元，用于通过串行总线向RF /模拟电路提供控制。 由于这两个循环在DVGA的设计和配置中彼此相互作用，所以基于DC循环的操作模式来选择VGA循环的操作模式。 在DC循环通过捕获模式操作的时间段内，选择在捕获模式中与DC环路的带宽成反比地运行。 通过串行总线提供与RF /模拟电路中的一些或全部相关的控制。 版权所有（C）2010，JPO＆INPIT
-
公开(公告)号：JP2010282637A
公开(公告)日：2010-12-16
申请号：JP2010157075
申请日：2010-07-09
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： SIH GILBERT C , ZOU QUIZHEN , JHA SANJAY K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI CHARLES E , KANTAK PRASHANT A
CPC classification number: G06F12/0886 , G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3885 , G06F9/3893 , G06F15/7807
Abstract: PROBLEM TO BE SOLVED: To provide a digital signal processor which enhances performance and availability. SOLUTION: A DSP includes a set of three data buses over which data may be exchanged with a register bank 120 and three data memories 102, 103 and 104. The register bank 120 may be used that includes registers accessible by at least two processing units 128 and 130. An instruction fetch unit 156 may include that receives instructions of variable length stored in an instruction memory 152. The instruction memory 152 may be separated from the set of three data memories 102, 103 and 104. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：提供一种提高性能和可用性的数字信号处理器。 解决方案：DSP包括一组三条数据总线，数据可以通过该组三个数据总线与寄存器组120和三个数据存储器102,103和104进行交换。可以使用寄存器组120，其包括可由至少两个 处理单元128和130.指令提取单元156可以包括接收存储在指令存储器152中的可变长度的指令。指令存储器152可以与三组数据存储器102,103和104分离。 ：（C）2011，JPO＆INPIT
-
公开(公告)号：JP2009010959A
公开(公告)日：2009-01-15
申请号：JP2008177384
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture capable of providing the required signal gain and DC offset correction. SOLUTION: A direct downconversion receiver architecture has a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收器架构具有DC环路，用于消除信号分量的DC偏移，提供一系列增益的数字可变增益放大器（DVGA），提供增益控制的自动增益控制（AGC）回路 用于DVGA和RF /模拟电路，以及串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。 版权所有（C）2009，JPO＆INPIT
-
公开(公告)号：JP2011083000A
公开(公告)日：2011-04-21
申请号：JP2010248701
申请日：2010-11-05
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： SIH GILBERT C , TIAN YUSHI
CPC classification number: H04N19/423 , H04N19/43 , H04N19/503 , H04N19/61
Abstract: PROBLEM TO BE SOLVED: To implement high-speed encoding and decoding for processing digital video data. SOLUTION: A device for processing digital video data, such as an encoder, a decoder or an encoder/decoder (CODEC) 20 makes the use of an innovative architecture in which functionality is partitioned between an embedded processor, a digital signal processor and dedicated hardware to achieve increased performance. In addition, the device includes a programmable video direct memory access (VDMA) controller 26 to retrieve video data from memory in response to a command specifying a multidimensional block of video data. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：实现用于处理数字视频数据的高速编码和解码。 解决方案：用于处理诸如编码器，解码器或编码器/解码器（CODEC）20之类的数字视频数据的装置使得使用创新架构，其中功能被分配在嵌入式处理器，数字信号处理器 和专用硬件来实现增加的性能。 此外，该设备包括可编程视频直接存储器访问（VDMA）控制器26，以响应于指定视频数据的多维块的命令来从存储器检索视频数据。 版权所有（C）2011，JPO＆INPIT
-
Patent Agency Ranking
公开(公告)号：JP2008295076A
公开(公告)日：2008-12-04
申请号：JP2008177383
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To obtain a direct down converting receiver architecture having a DC loop for removing a DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing gain control relating to the DVGA and RF/analog circuits, and a serial bus interface (SBI) unit for providing control relating to the RF/analog circuits via a serial bus. SOLUTION: The DVGA is to be effectively designed and disposed. Since these two loops mutually performs interaction, an operation mode of the VGA loop is to be selected based on an operation mode of the DC loop. Selection is made so as to be in inverse proportion to bandwidth of the DC loop in a captured mode while the DC loop is operated by the captured mode. Control is to be provided to some or all of the RF/analog circuits via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：为了获得具有用于从信号分量中去除DC偏移的DC回路的直接下变频接收机架构，用于提供增益范围的数字可变增益放大器（DVGA），自动增益控制（AGC） ）环路，用于执行与DVGA和RF /模拟电路相关的增益控制;以及串行总线接口（SBI）单元，用于经由串行总线提供与RF /模拟电路相关的控制。
解决方案：DVGA要有效设计和处理。 由于这两个环路相互进行交互，所以基于DC循环的操作模式来选择VGA环路的操作模式。 在捕捉模式下，直流环路被捕捉模式操作时，进行与直流回路的带宽成反比例的选择。 将通过串行总线向部分或全部RF /模拟电路提供控制。 版权所有（C）2009，JPO＆INPIT
-
7.发明申请
公开(公告)号：WO2005089116A3
公开(公告)日：2007-01-25
申请号：PCT/US2005006907
申请日：2005-03-02
Applicant: QUALCOMM INC , SIH GILBERT C , HSU DE D , LEE WAY-SHING , CHEN XUFENG
Inventor： SIH GILBERT C , HSU DE D , LEE WAY-SHING , CHEN XUFENG
IPC: G06F9/30
CPC classification number: G06F9/30014 , G06F9/30032 , G06F9/3875 , G06F9/3885 , G06F9/3893
Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.
Abstract translation: 描述了具有改进性能的DSP架构。 在示例性架构中，DSP包括两个MAC单元和两个ALU，其中一个ALU替换两个MAC单元之一的加法器。 该DSP可以被配置为以双MAC /单ALU配置，单MAC /双ALU配置或双MAC /双ALU配置来操作。 这种灵活性允许DSP处理各种类型的信号处理操作，并提高可用硬件的利用率。 DSP架构还包括流水线寄存器，其分解关键路径，并允许以更高的时钟速度进行操作以获得更高的吞吐量。
-
公开(公告)号：WO03049454A3
公开(公告)日：2003-09-04
申请号：PCT/US0238666
申请日：2002-12-03
Applicant: QUALCOMM INC
Inventor： SIH GILBERT C , TIAN YUSHI
CPC classification number: H04N19/423 , H04N19/43 , H04N19/503 , H04N19/61
Abstract: In general, the invention is directed toward a device for processing digital video data, such as an encoder, a decoder or an encoder/decoder (CODEC). The device makes use of an innovative architecture in which functionality is partitioned between an embedded processor, a digital signal processor and dedicated hardware to achieve increased performance. In addition, the device includes a programmable video direct memory access (VDMA) controller to retrieve video data from memory in response to a command specifying a multidimensional block of video data.
Abstract translation: 通常，本发明针对用于处理数字视频数据的设备，诸如编码器，解码器或编码器/解码器（CODEC）。 该器件采用了创新的架构，其功能分为嵌入式处理器，数字信号处理器和专用硬件，以提高性能。 另外，该设备包括可编程视频直接存储器访问（VDMA）控制器，以响应指定视频数据的多维块的命令从存储器检索视频数据。
-
公开(公告)号：WO02061453A3
公开(公告)日：2003-02-13
申请号：PCT/US0204991
申请日：2002-01-31
Applicant: QUALCOMM INC
Inventor： WILBORN THOMAS BRIAN , PATEL SHIMMAN , SIH GILBERT C , ABRISHAMKAR FARROKH
CPC classification number: G01S11/02
Abstract: A velocityx estimate is determined from a recevied signal by counting the number of times a signal in one multipath crosses a predetermined threshold in a given amount of time. A signal is received and a single multipath is extracted from the received signal. Instantaneous envelope values of the extracted multipath are calculated. A plurality of the instantaneous envelope valures are used to calculate a running RMS value. A level crossing threshold is determined using the running RMS value. The number of times the instantaneous envelope value crosses the level crossing threshold is counted. The number of level crossings is mapped to a velocity estimate.
Abstract translation: 通过计算一个多径中的信号在给定的时间量内跨越预定阈值的次数，从接收信号确定速度估计。 接收信号并从接收信号中提取单个多路径。 计算提取的多路径的瞬时包络值。 多个瞬时包络线被用于计算正在运行的RMS值。 使用正在运行的RMS值来确定级别交叉阈值。 计算瞬时包络值跨越等级交叉阈值的次数。 级别交叉点的数量映射到速度估计。
-
公开(公告)号：EP1763739A4
公开(公告)日：2008-07-16
申请号：EP05724448
申请日：2005-03-02
Applicant: QUALCOMM INC
Inventor： SIH GILBERT C , HSU DE D , LEE WAY-SHING , CHEN XUFENG
CPC classification number: G06F9/30014 , G06F9/30032 , G06F9/3875 , G06F9/3885 , G06F9/3893
Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.
-
-
-
-
-
-
-
-
-
Search Results
236
records
(took 0.025 seconds)
