公开(公告)号：US20140193948A1

公开(公告)日：2014-07-10

申请号：US14202756

申请日：2014-03-10

Applicant: RAYTHEON COMPANY

Inventor： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Adam M. Kennedy

IPC: B81C1/00

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract translation: 一种形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括残留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的所述第一和第二组的组合厚度在所述器件晶片和所述盖晶片接合时限定了整合的接合间隙控制结构。

公开(公告)号：US20140175590A1

公开(公告)日：2014-06-26

申请号：US13721545

申请日：2012-12-20

Applicant: RAYTHEON COMPANY

Inventor： Roland Gooch ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas Allan Kocian ,  Buu Diep

IPC: H01L31/0203

CPC classification number: H01L31/0203 ,  B81B7/0038 ,  G01J5/0285 ,  G01J5/045 ,  G01J5/0875 ,  H01L23/26 ,  H01L27/14618 ,  H01L27/14649 ,  H01L2924/0002 ,  Y10T29/4998 ,  Y10T428/24521 ,  H01L2924/00

Abstract: A wafer level vacuum packaged (WLVP) device having a first substrate having an array of detectors and a second substrate bonded to the first substrate having a plurality of protrusions and a plurality of getter material members projecting outwardly from a sidewall of the protrusions members are disposed at oblique angles to the sidewalls and have ends extending into gaps between the protrusions. The device is formed by: forming protrusions into a surface of a substrate; and depositing getter material by physical vapor deposition from an evaporating source of the getter material at an oblique angle to the sidewalls, atoms of the getter material initially forming nucleation sites on the sidewalls with subsequent atoms attaching to the nucleation sites and shadowing area surrounding each nucleation site, the getter material thereby growing into structures towards the evaporating source.

Abstract translation: 晶片级真空封装（WLVP）器件具有具有检测器阵列的第一衬底和与第一衬底接合的第二衬底，其具有多个突起和从突出构件的侧壁向外突出的多个吸气材料构件 与侧壁成倾斜的角度并且具有延伸到突起之间的间隙的端部。 该装置通过以下方式形成：将突起形成在基板的表面中; 并且通过物理气相沉积从吸气材料的蒸发源以与侧壁倾斜的角度沉积吸气剂材料，吸气材料的原子最初在侧壁上形成成核位点，随后的原子附着于成核位置和围绕每个成核的阴影区域 吸气剂材料因此生长成朝向蒸发源的结构。

公开(公告)号：US11284025B2

公开(公告)日：2022-03-22

申请号：US16890483

申请日：2020-06-02

Applicant: Raytheon Company

Inventor： Neil R. Malone ,  Micky Harris ,  Adam M. Kennedy ,  George Paloczi ,  John L. Vampola ,  Christian M. Boemler

IPC: H04N5/355 ,  H04N5/378 ,  H04N5/3745

Abstract: A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

公开(公告)号：US09708181B2

公开(公告)日：2017-07-18

申请号：US15048106

申请日：2016-02-19

Applicant: Raytheon Company

Inventor： Adam M. Kennedy ,  Buu Q. Diep ,  Stephen H. Black ,  Tse E. Wong ,  Thomas Allan Kocian ,  Gregory D. Tracy

IPC: H01L21/50 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00333 ,  B81B7/0048 ,  B81B7/0051 ,  B81B2201/0207 ,  B81C1/00825 ,  B81C2203/035

Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

公开(公告)号：US20170131475A1

公开(公告)日：2017-05-11

申请号：US14938361

申请日：2015-11-11

Applicant: RAYTHEON COMPANY

Inventor： Justin Gordon Adams Wehner ,  Duane D. Smith ,  Edward Peter Gordon Smith ,  Adam M. Kennedy

IPC: G02B6/293 ,  G02F1/157

CPC classification number: G02B6/29395 ,  G01J5/045 ,  G01J5/0831 ,  G01J5/522 ,  G02B6/29358 ,  G02B6/29389 ,  G02F1/157 ,  G02F2203/11 ,  H01L27/00 ,  H01L28/00 ,  H04N17/002

Abstract: A scene projector including an array of light emitting pixels, a tunable filter element, and a spatial light modulator. The tunable filter element is optically coupled to the array of light emitting pixels such that light emitted from the array of light emitting pixels is passed through the tunable filter element as filtered light. The spatial light modulator is optically coupled to the array of light emitting pixels and is configured to generate transmitted light by interacting with the filtered light to control at least one of an amplitude, a phase, and a polarization of the filtered light.

公开(公告)号：US20170011977A1

公开(公告)日：2017-01-12

申请号：US15270145

申请日：2016-09-20

Applicant: RAYTHEON COMPANY

Inventor： Roland W. Gooch ,  Buu Q. Diep ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas A. Kocian

IPC: H01L23/10 ,  H01L27/146 ,  H01L23/26 ,  B81B7/00 ,  B81C1/00

CPC classification number: H01L23/10 ,  B81B7/0038 ,  B81B2201/0207 ,  B81C1/00269 ,  B81C2203/035 ,  H01L21/52 ,  H01L21/76841 ,  H01L23/26 ,  H01L23/49866 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

Abstract translation: 电子装置及其制造方法。 一种或多种方法可以包括提供具有空腔和围绕空腔的表面的盖晶片和具有检测器装置和参考装置的装置晶片。 在某些实例中，可以将钛材料的阻焊层沉积到盖晶片的表面上。 可以进一步激活钛材料的阻焊层作为吸气剂。 在各种示例中，盖晶片和器件晶片可以使用焊料接合在一起，并且钛材料的阻焊层可以防止焊料接触盖晶片的表面。

公开(公告)号：US09520332B2

公开(公告)日：2016-12-13

申请号：US14736042

申请日：2015-06-10

Applicant: RAYTHEON COMPANY

Inventor： Roland W. Gooch ,  Buu Q. Diep ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas A. Kocian

IPC: H01L23/48 ,  H01L23/20 ,  H01L21/00 ,  H01L21/30 ,  H01L23/10 ,  H01L23/498 ,  H01L21/768 ,  B81B7/00 ,  H01L23/26 ,  B81C1/00 ,  H01L21/52 ,  H01L27/146

CPC classification number: H01L23/10 ,  B81B7/0038 ,  B81B2201/0207 ,  B81C1/00269 ,  B81C2203/035 ,  H01L21/52 ,  H01L21/76841 ,  H01L23/26 ,  H01L23/49866 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

公开(公告)号：US20160340179A1

公开(公告)日：2016-11-24

申请号：US15227181

申请日：2016-08-03

Applicant: RAYTHEON COMPANY

Inventor： Roland W. Gooch ,  Buu Q. Diep ,  Stephen H. Black ,  Thomas A. Kocian ,  Adam M. Kennedy

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00325 ,  B05D5/061 ,  B81B7/0067 ,  B81B2201/0207 ,  B81C2203/0118

Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.

Abstract translation: 提供了通过盖晶片的抗反射涂层引起的减少晶片弓的方法。 该方法可以利用其中具有至少一个开口的荫罩，其位于帽晶片中的相对凹陷区域。 该方法还可以包括将至少一层抗反射涂层材料通过荫罩沉积到盖晶片的平面侧上，以在平面侧上提供不连续的涂层。

公开(公告)号：US20160167959A1

公开(公告)日：2016-06-16

申请号：US15048106

申请日：2016-02-19

Applicant: Raytheon Company

Inventor： Adam M. Kennedy ,  Buu Q. Diep ,  Stephen H. Black ,  Tse E. Wong ,  Thomas Allan Kocian ,  Gregory D. Tracy

IPC: B81C1/00

CPC classification number: B81C1/00333 ,  B81B7/0048 ,  B81B7/0051 ,  B81B2201/0207 ,  B81C1/00825 ,  B81C2203/035

Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract translation: 密封包装，其具有设置在晶片结构上的装置和骨架到装置晶片上的盖结构。 器件晶片包括：衬底; 设置在所述装置周围的基板的表面部分上的金属环和设置在所述金属环上的接合材料。 金属环横向延伸超过接合材料的内边缘和外边缘中的至少一个。 金属环的第一层包括具有比衬底的表面部分更高的延展性的应力消除缓冲层，并且具有大于接合材料的宽度的宽度。 金属环横向延伸超出接合材料的内边缘和外边缘中的至少一个。 应力消除缓冲层的热膨胀系数大于衬底表面部分的膨胀系数，小于接合材料的膨胀系数。

公开(公告)号：US09334154B2

公开(公告)日：2016-05-10

申请号：US14456476

申请日：2014-08-11

Applicant: Raytheon Company

Inventor： Adam M. Kennedy ,  Buu Q. Diep ,  Stephen H. Black ,  Tse E. Wong ,  Thomas Allan Kocian ,  Gregory D. Tracy

IPC: H01L23/552 ,  B81B7/00

CPC classification number: B81C1/00333 ,  B81B7/0048 ,  B81B7/0051 ,  B81B2201/0207 ,  B81C1/00825 ,  B81C2203/035

Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract translation: 密封包装，其具有设置在晶片结构上的装置和骨架到装置晶片上的盖结构。 器件晶片包括：衬底; 设置在所述装置周围的基板的表面部分上的金属环和设置在所述金属环上的接合材料。 金属环横向延伸超过接合材料的内边缘和外边缘中的至少一个。 金属环的第一层包括具有比衬底的表面部分更高的延展性的应力消除缓冲层，并且具有大于接合材料的宽度的宽度。 金属环横向延伸超出接合材料的内边缘和外边缘中的至少一个。 应力消除缓冲层的热膨胀系数大于衬底表面部分的膨胀系数，小于接合材料的膨胀系数。