GETTER STRUCTURE FOR WAFER LEVEL VACUUM PACKAGED DEVICE
    32.
    发明申请
    GETTER STRUCTURE FOR WAFER LEVEL VACUUM PACKAGED DEVICE 审中-公开
    水平真空包装设备的结构

    公开(公告)号:US20140175590A1

    公开(公告)日:2014-06-26

    申请号:US13721545

    申请日:2012-12-20

    Abstract: A wafer level vacuum packaged (WLVP) device having a first substrate having an array of detectors and a second substrate bonded to the first substrate having a plurality of protrusions and a plurality of getter material members projecting outwardly from a sidewall of the protrusions members are disposed at oblique angles to the sidewalls and have ends extending into gaps between the protrusions. The device is formed by: forming protrusions into a surface of a substrate; and depositing getter material by physical vapor deposition from an evaporating source of the getter material at an oblique angle to the sidewalls, atoms of the getter material initially forming nucleation sites on the sidewalls with subsequent atoms attaching to the nucleation sites and shadowing area surrounding each nucleation site, the getter material thereby growing into structures towards the evaporating source.

    Abstract translation: 晶片级真空封装(WLVP)器件具有具有检测器阵列的第一衬底和与第一衬底接合的第二衬底,其具有多个突起和从突出构件的侧壁向外突出的多个吸气材料构件 与侧壁成倾斜的角度并且具有延伸到突起之间的间隙的端部。 该装置通过以下方式形成:将突起形成在基板的表面中; 并且通过物理气相沉积从吸气材料的蒸发源以与侧壁倾斜的角度沉积吸气剂材料,吸气材料的原子最初在侧壁上形成成核位点,随后的原子附着于成核位置和围绕每个成核的阴影区域 吸气剂材料因此生长成朝向蒸发源的结构。

    Digital pixel having high sensitivity and dynamic range

    公开(公告)号:US11284025B2

    公开(公告)日:2022-03-22

    申请号:US16890483

    申请日:2020-06-02

    Abstract: A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

    Hermetically sealed package having stress reducing layer

    公开(公告)号:US09708181B2

    公开(公告)日:2017-07-18

    申请号:US15048106

    申请日:2016-02-19

    Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

    HERMETICALLY SEALED PACKAGE HAVING STRESS REDUCING LAYER
    39.
    发明申请
    HERMETICALLY SEALED PACKAGE HAVING STRESS REDUCING LAYER 有权
    具有应力减少层的人造密封包装

    公开(公告)号:US20160167959A1

    公开(公告)日:2016-06-16

    申请号:US15048106

    申请日:2016-02-19

    Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

    Abstract translation: 密封包装,其具有设置在晶片结构上的装置和骨架到装置晶片上的盖结构。 器件晶片包括:衬底; 设置在所述装置周围的基板的表面部分上的金属环和设置在所述金属环上的接合材料。 金属环横向延伸超过接合材料的内边缘和外边缘中的至少一个。 金属环的第一层包括具有比衬底的表面部分更高的延展性的应力消除缓冲层,并且具有大于接合材料的宽度的宽度。 金属环横向延伸超出接合材料的内边缘和外边缘中的至少一个。 应力消除缓冲层的热膨胀系数大于衬底表面部分的膨胀系数,小于接合材料的膨胀系数。

    Hermetically sealed package having stress reducing layer
    40.
    发明授权
    Hermetically sealed package having stress reducing layer 有权
    密封包装,具有减压层

    公开(公告)号:US09334154B2

    公开(公告)日:2016-05-10

    申请号:US14456476

    申请日:2014-08-11

    Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

    Abstract translation: 密封包装,其具有设置在晶片结构上的装置和骨架到装置晶片上的盖结构。 器件晶片包括:衬底; 设置在所述装置周围的基板的表面部分上的金属环和设置在所述金属环上的接合材料。 金属环横向延伸超过接合材料的内边缘和外边缘中的至少一个。 金属环的第一层包括具有比衬底的表面部分更高的延展性的应力消除缓冲层,并且具有大于接合材料的宽度的宽度。 金属环横向延伸超出接合材料的内边缘和外边缘中的至少一个。 应力消除缓冲层的热膨胀系数大于衬底表面部分的膨胀系数,小于接合材料的膨胀系数。

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