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    33.
    发明专利
    未知

    公开(公告)号：DE69333890D1

    公开(公告)日：2005-12-01

    申请号：DE69333890

    申请日：1993-05-18

    Applicant: SONY CORP

    Inventor： OKUMOTO KOJI ,  MATSUNO KATSUMI ,  SHIONO TORU ,  SENUMA TOSHITAKA ,  FUKUDA TOKUYA ,  TAKADA SHINJI

    IPC: G01R31/3185 ,  G01R31/318 ,  G06F11/26

    Abstract: A method of testing an electronic apparatus (1) which eliminates a control signal line for setting an integrated circuit (IC1, IC2, IC3) to a test mode and a test mode select terminal of an external terminal section and wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation. In each of the integrated circuits, a boundary scan control circuit (8) discriminates a category code (Ci) at the beginning of data inputted from a serial input terminal (SI) to control a pair of switching circuits (SW1, SW2). When the category code represents a test mode, predetermined terminals (b) of the switching circuits (SW1, SW2) are selected so that input data are sent out to boundary scan cells (BC1 to BC8). Fetching of parallel data from parallel input terminals (PI1 to PI4) and transfer to the boundary scan cells (BC5 to BC8) are performed at one time.

    BUS MANAGEMENT METHOD
    34.
    发明专利
    BUS MANAGEMENT METHOD 未知

    公开(公告)号：CA2144970C

    公开(公告)日：2004-09-28

    申请号：CA2144970

    申请日：1994-07-19

    Applicant: SONY CORP

    Inventor： MATSUNO KATSUMI ,  KUBOTA ICHIRO ,  HAYASHI MINOBU ,  SHIMA HISATO

    IPC: H04L12/40 ,  H04L12/403 ,  H04L12/64

    Abstract: A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

    37.
    发明专利
    未知

    公开(公告)号：DE69429908T2

    公开(公告)日：2002-09-19

    申请号：DE69429908

    申请日：1994-07-19

    Applicant: SONY CORP

    Inventor： MATSUNO KATSUMI ,  KUBOTA ICHIRO ,  HAYASHI MINOBU ,  SHIMA HISATO

    IPC: H04L12/40 ,  H04L12/403 ,  H04L12/64

    Abstract: A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

    38.
    发明专利
    未知

    公开(公告)号：DE69331292T2

    公开(公告)日：2002-06-13

    申请号：DE69331292

    申请日：1993-01-22

    Applicant: SONY CORP

    Inventor： YAMAMOTO IWAO ,  MATSUNO KATSUMI

    IPC: G06F11/28 ,  G06F9/06 ,  G06F9/38 ,  G06F9/445 ,  G06F9/46 ,  G06F9/48 ,  G06F11/00 ,  G06F11/20 ,  G06F9/26

    Abstract: An electronic apparatus (10) which includes a CPU (1), a ROM (2), a RAM (3), an input port (4), a data bus (5), an address bus (6), a patching portion address register (7) and a patching interrupt vector register (8) which are connected to the data bus (5), a comparator (9) which compares a coincidence with the address stored in the address register (7) and an address on the address bus (6) and supplies an interrupt to an interrupt control portion of the CPU (1) which is also supplied with other interrupts for other processing. Further, an external storage device (20), connected to the input port (4), supplies a main program bug patching information which is stored in the RAM (3), which includes a stack area (32) in which there are saved data written in the address register (7) and the patching interrupt register (8), so that patching of program bugs can be carried out even during an interrupt.

    39.
    发明专利
    未知

    公开(公告)号：DE69228272D1

    公开(公告)日：1999-03-11

    申请号：DE69228272

    申请日：1992-05-18

    Applicant: SONY CORP

    Inventor： SHIMADA KEIICHIRO ,  MATSUNO KATSUMI ,  FURUI SUNAO

    IPC: G06F12/06 ,  G06F9/06 ,  G06F9/26 ,  G06F9/445 ,  G06F11/00 ,  G06F11/08 ,  G06F11/14 ,  G06F9/44 ,  G06F11/20

    Abstract: A micro-controller integrated on a single substrate and which includes a read-only information memory (15) for storing firmware, an address controller (14) for performing address control, and an input port (12) for inputting information supplied thereto from a source (11) external to the substrate further incorporates a correcting information storage memory (100) for receiving correcting information input thereto from the source (11) external to the substrate through the input port (12) and storing the correcting information upon an initialization of the micro-controller, wherein the correcting information is indicative of a modification for a defective information part stored in the read-only information storage memory (15), and a switching circuit (200) for selectively switching the access by the address controller (14) from the defective information part in the read-only information storage memory (15) to the correcting information in the correcting information storage memory (100).

    ELECTRONIC APPARATUS AND METHOD FOR PATCHING A FIXED INFORMATION
    40.
    发明专利
    ELECTRONIC APPARATUS AND METHOD FOR PATCHING A FIXED INFORMATION 未知

    公开(公告)号：CA2087696A1

    公开(公告)日：1993-07-25

    申请号：CA2087696

    申请日：1993-01-20

    Applicant: SONY CORP

    Inventor： YAMAMOTO IWAO ,  MATSUNO KATSUMI

    IPC: G06F11/28 ,  G06F9/06 ,  G06F9/38 ,  G06F9/445 ,  G06F9/46 ,  G06F9/48 ,  G06F11/00 ,  G06F12/10

    Abstract: PATENT An electronic apparatus which includes a CPU, a ROM, a RAM, an input port, a data bus, an address bus, a patching portion address register and a patching interrupt vector register which are connected to the data bus, a comparator which compares a coincidence with the address stored in the address register and an address on the address bus and supplies an interrupt to an interrupt control portion of the CPU which is also supplied with other interrupts for other processing. Further, an external storage device, connected to the input port, supplies a main program bug patching information which is stored in the RAM, which includes a stack area in which there are saved data written in the address register and the patching interrupt register, so that patching of program bugs can be carried out even during an interrupt.

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