公开(公告)号：FR2895556A1

公开(公告)日：2007-06-29

申请号：FR0513326

申请日：2005-12-26

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  JACQUET FRANCOIS

IPC: G11C11/419

Abstract: L'invention concerne un dispositif, ainsi qu'un procédé de mise en oeuvre correspondant, de stockage d'informations à mémoires SRAM, alimenté par une tension VDD et comprenant :- une matrice de cellules de base organisées en colonnes de base, et- au moins une colonne miroir de cellules miroir, susceptibles de simuler le comportement des cellules d'une colonne de base,L'invention est caractérisée en ce que le dispositif comprend en outre :- Des moyens d'émulation, dans une colonne miroir, de la cellule la plus contraignante d'une colonne de base,- Des moyens de variation de la tension d'alimentation miroir (VDDMMOCK) de la colonne miroir, et- Des moyens pour recopier la tension d'alimentation miroir dans la colonne de base émulée.

公开(公告)号：DE60219100D1

公开(公告)日：2007-05-10

申请号：DE60219100

申请日：2002-05-06

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  FOURNEL RICHARD ,  THOMAS SIGRID

IPC: G11C16/04

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

公开(公告)号：FR2859327A1

公开(公告)日：2005-03-04

申请号：FR0310322

申请日：2003-08-29

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE

IPC: G11C16/12 ,  H03K17/16 ,  G11C5/14

Abstract: The switching circuit comprises three circuits allowing the connection between the node and one of three other nodes which provide the three voltages. Control ensures a mutually exclusive switching mode preventing any crossover current. The switching circuit is provided to switch a node to one of three possible supply voltages (GND, V33, V55) as a function of two control signals (ERASE, PROG). The device comprises three circuits allowing the connection between the node and one of three other nodes which provide the three voltages. The device is controlled by control signals CDENMOS, CDEPMOS, Z1 & Z2, READPATH & PROGPATH, which together ensure a mutually exclusive switching mode and preventing any crossover current. The device uses MOS transistors with a low nominal voltage, which is lower than that of the highest switched voltage.

公开(公告)号：FR2823900B1

公开(公告)日：2003-08-15

申请号：FR0105343

申请日：2001-04-20

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  FOURNEL RICHARD

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/66

Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

公开(公告)号：FR2819954A1

公开(公告)日：2002-07-26

申请号：FR0100953

申请日：2001-01-24

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE

IPC: G05F1/46 ,  G05F3/24 ,  H03K17/56 ,  G11C16/12

Abstract: The invention concerns a control device comprising a circuit generating REF reference voltages (VPOL1, V POL2) comprising three P-type MOS transistors (M12, M13 and M14) connected in series between a high-voltage input node (EHV) and the earth (GND), and supplying on the drain and the source of the middle transistor (M13) reference voltages (VPOL1, V POL2). Said device comprises means for controlling the reference transistors either, in a first operating mode, to force the first reference transistor (M12) in current source, the second reference transistor (M13) in off-state and short-circuit the third reference transistor (M14) to the earth, or, in a second operating mode, in connecting each of said transistors in diode, their gate and their drain being connected, on the basis of a logic control signal (/WR). Thus, the resulting reference voltages in output are based on said logic signal.

公开(公告)号：FR2812753A1

公开(公告)日：2002-02-08

申请号：FR0010287

申请日：2000-08-03

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE

IPC: H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  G11C11/40

Abstract: The point memory comprises a p-type MOS transistor whose gate is not electrically connected, and which in the ring implementation comprises a central electrode (10), surrounded by the gate (20) and a peripheral electrode (30). The central electrode (10) is the drain electrode, and the peripheral electrode (30) is the source electrode. The peripheral electrode comprises at least two, in particular eight contact points (C1,...,C8). An integrated circuit comprises at least one point memory of read-only type as proposed. The integrated circuit also comprises a control circuit for applying programming and reading voltages to the point memory.