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公开(公告)号：DE60219100D1
公开(公告)日：2007-05-10
申请号：DE60219100
申请日：2002-05-06
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , FOURNEL RICHARD , THOMAS SIGRID
IPC: G11C16/04
Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.
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公开(公告)号：FR2823362A1
公开(公告)日：2002-10-11
申请号：FR0104750
申请日：2001-04-06
Applicant: ST MICROELECTRONICS SA
Inventor： AITOUARAB LEILA , THOMAS SIGRID
Abstract: The device comprises a differential amplifier with inputs (e1,e2) connected to the bit lines of a memory cell (Cmem) and a reference cell (Cref), respectively, a circuit for precharging the output of the differential amplifier to a predetermined voltage level (V1) which is intermediate between the high logic level and the low logic level, and a Schmitt trigger circuit, which is an inverter with a threshold, delivering the output signal DATAOUT. The intermediate voltage level corresponds to the means of high and low logic levels, which is (Vdd/2). The output precharge circuit comprises an upper branch with two p-MOS transistors and a lower branch with two n-MOS transistors; each branch comprises a transistor connected as a diode and a transistor controlled by a precharge signal. The device also comprises an equilibration circuit for equilibrating the two inputs (e1,e2) of the differential amplifier, which is activated in the precharge phase. The output precharge circuit is deactivated after the equilibration circuit. An integrated circuit comprises the device for reading memory cells, which are of SRAM type.
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公开(公告)号：FR2829280B1
公开(公告)日：2004-09-24
申请号：FR0111485
申请日：2001-09-05
Applicant: ST MICROELECTRONICS SA
Inventor： THOMAS SIGRID
Abstract: A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.
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公开(公告)号：FR2829280A1
公开(公告)日：2003-03-07
申请号：FR0111485
申请日：2001-09-05
Applicant: ST MICROELECTRONICS SA
Inventor： THOMAS SIGRID
Abstract: A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.
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公开(公告)号：FR2817413B1
公开(公告)日：2003-02-28
申请号：FR0015447
申请日：2000-11-29
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , THOMAS SIGRID
IPC: G11C5/14 , G11C8/08 , G11C16/04 , G11C16/30 , H03K19/003 , H03K17/0412 , H03K17/56
Abstract: A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.
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Patent Agency Ranking
公开(公告)号：FR2817413A1
公开(公告)日：2002-05-31
申请号：FR0015447
申请日：2000-11-29
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , THOMAS SIGRID
IPC: G11C5/14 , G11C8/08 , G11C16/04 , G11C16/30 , H03K19/003 , H03K17/0412 , H03K17/56
Abstract: The switching device comprises a voltage-shift type switching circuit for switching a higher supply voltage (HV) on at least one output line (L1) of capacitve type, a transistor (M30) for switching a lower supply voltage Vcc(V1) on the same output line, and a control circuit (4) for controlling the drop of the gate voltage of the switching transistor (M30) from the higher supply voltage to the ground potential subjected to the drop of the output line voltage from the higher supply voltage in the lower supply voltage. The switchihng circuit comprises two branches; the first branch comprising a loading transistor (M10) connected to the higher supply voltage terminal (HV), a switching transistor (M13) connected to the ground and receiving as the gate voltage the inverse of control voltage (CTRL), one or more cascade transistors (M11,M12) connected between the two transistors, and a repeater transistor (M40) connected in series in the same branch and associated with the output line by the intermediary of node (N11) providing the gate signal to the lower supply voltage switching transistor (M30) directly connected to the output line; the second branch comprises a set of transistors starting with a loading transistor (M20); and a transistor (M50) is connected as a resistor between the two branches for favouring the polarization of the cascade transistors. The voltage-shift circuit (40) applies a biasing voltage (Vbias2) as the gate voltage to the repeater transistor (M40) of the first branch of the switching circuit. The circuit (40) comprises two branches; the first branch comprises a transistor (M41) with the gate and the drain connected together to a polarization node providing the first biasing voltage (Vbias1) and a transistor (M42) connected as a diode; the second branch comprises a transistor (M43) connected as a current mirror with the transistor (M41) of the first branch, and a set of transistors (M44,M45) connected as diodes between the transistor (M43) and the output line. The lower supply voltage (V1) is equal to the logic supply voltage (Vcr). In the second embodiment, the switching device comprises a supplementary loading transistor connected between the higher supply voltage terminal and the output line, and is controlled by the same signal as the loading transistor of the first branch of the switching circuit. The integrated circuit comprises the switching device associated with at least one current-conducting output line. The integrated circuit of a read-only memory store has output lines which are the lines for selecting memory cells. The memory store is of type FAMOS or FLASH-EPROM, and the selection lines are for rows of memory cells.
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公开(公告)号：DE60223625D1
公开(公告)日：2008-01-03
申请号：DE60223625
申请日：2002-06-14
Applicant: ST MICROELECTRONICS SA
Inventor： THOMAS SIGRID
IPC: G11C17/12 , H01L21/8246 , H01L27/112
Abstract: The read-only memory store is constituted of cells wherein each programmed cell (20) comprises a series connection of a memory element (22) and a selection transistor (4) connected between a selection line (SL) and a bit line (BL). The selection transistor is of MOS type and its gate (5) is connected to a read line (RL). The memory element (22) is no longer a MOS transistor as in known programmable cells, but an active zone (26) which is uniformly n-type doped and acts as a resistance. The memory element of a non-programmed cell is p-MOS transistor whose gate is connected to that of the selection transistor, or left unconnected as in programmable cells. The read-only memory is implemented in the same integrated circuit chip as a programmable memory, where the selection lines of the read-only memory and the programmable memory are connectable to a selection supply voltage (VDD), and the selection lines of the programmable memory are selectively connectable to a write supply voltage (VPP), which is higher than the selection supply voltage. A method for making the read-only memory in a monocrystalline semiconductor substrate comprises the steps of defining the active zones (11,26) in the same dimension, forming an insulated line (5) above the active zone (11), implanting the exposed parts of the active zones, depositing an insulator on the obtained structure, opening the insulator so to partially expose the active zones in the neighbourhood of each extremity, and forming the selection lines (SL) in contact with the active zones (26), conducting links (9) so to pair up the active zones (11,26) and the bit lines (BL) in contact with the active zones (11).
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公开(公告)号：FR2824413A1
公开(公告)日：2002-11-08
申请号：FR0106091
申请日：2001-05-07
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , FOURNEL RICHARD , THOMAS SIGRID
Abstract: The memory store is organized in words according to an array of rows and columns, and the selection of a word is ensured by the signals for selecting a row and a column (Selrow,Selcol), where the signals are delivered by two address decoders (DECX,DECYm). Each memory-cell word (M0,0) regroups several, in particular 8 for 8-bit word, memory cells (C0,...,C7) on the same row, and each cell comprises a memory transistor of MOS type with a control gate and two channel electrodes the drainn and the source; the control gates of the cells of each row are connected together to a gate control line (CG0), and the drain of each cell is connected to the respective bit line (B10,...,B17). Each word comprises a word-selecting transistor (TS0,0) by the source, and is controlled by the low-voltage selection signals (SelRow,SelCol). The gate control lines (CG0,...Cgm-1) are controlled by a polarization circuit (1) receiving the address selection signals. The gate control lines are regrouped at least two by two, and each group is controlled by a higher-voltage switching circuit of the polarization circuit. The gate control lines put together correspond to the to the neighbouring rows. The higher-voltage switching circuit applies either the higher voltage (Vpp) in the case of the write instruction, or a stationary voltage (Vrepos) applied outside of the write operation. The level of stationary voltage is chosen as equal to the level of polarization voltage in the read mode. Each column of memory store comprises bit lines (B10,...,B17), connected to a write circuit (2) for writing (DATA-IN) and to a read circuit (3) for reading (DATA-OUT). The read circuit (3) comprises a precharge circuit associated with a detection circuit comprising differential amplfiers, and the precharge circuit receives an activation instruction before the start of a cycle or a succession of cycles of the read operations. The precharge circuit brings all bit lines to the same precharge voltage (Vpch). The memory store comprises an isolating circuit (EI) between the bit lines and the read circuit (3), which is activated during the write operations. An integrated circuit comprises the read-only memory store of specified architecture.
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公开(公告)号：FR2823362B1
公开(公告)日：2005-03-11
申请号：FR0104750
申请日：2001-04-06
Applicant: ST MICROELECTRONICS SA
Inventor： AITOUARAB LEILA , THOMAS SIGRID
Abstract: In a device for reading memory cells, a precharging circuit is connected to a memory cell to be read and to a reference cell associated with the memory cell to be read. The precharging circuit precharges the output of the differential amplifier to a predetermined voltage level. The reading device further includes an inverter having a high threshold and a low threshold connected to the output of the differential amplifier. The predetermined voltage level corresponds to an intermediate level between the high and low thresholds.
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公开(公告)号：FR2824413B1
公开(公告)日：2003-07-25
申请号：FR0106091
申请日：2001-05-07
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , FOURNEL RICHARD , THOMAS SIGRID
Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.
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