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    MEMORY DEVICE AND INTEGRATED CIRCUIT
    1.
    发明专利
    MEMORY DEVICE AND INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：JP2003152119A

    公开(公告)日：2003-05-23

    申请号：JP2002252983

    申请日：2002-08-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

    IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide an FAMOS memory location which can have at least three completely natural program levels. SOLUTION: An FAMOS memory location is provided with a single floating gate (GR) overlapping the active plane of a semiconductor substrate along contour (PF1, PF2) of at least two asymmetric overlaps in order to determine at least two electrodes in an active region. A memory location program means (MC, SW) applies a set of specified different voltages selectively to the electrodes such that at least three program logical levels are outputted to the memory location.

    Non-volatile programmable and electrically erasable memory with single layer of grid material
    3.
    发明专利
    Non-volatile programmable and electrically erasable memory with single layer of grid material 审中-公开
    具有单层网格材料的非易失性可编程和电可擦除存储器

    公开(公告)号：JP2003273257A

    公开(公告)日：2003-09-26

    申请号：JP2003057906

    申请日：2003-03-05

    Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

    Inventor： DRAY CYRILLE ,  GENDRIER PHILIPPE ,  FOURNEL RICHARD

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

    Abstract: PROBLEM TO BE SOLVED: To provide a memory device which overcomes the data holding problem caused by the thinness of its grid dielectric present in the interface between its STI-type isolation region and its grid material.
    SOLUTION: The semiconductor memory device comprises a non-volatile programmable and electrically erasable memory cell having a single layer of grid material. Also, the memory cell comprises a floating grid transistor and a control grid within an active semiconductor area which is formed in a region of a substrate and is delimited by an isolation region. The single layer of grid material wherein the floating grid is formed extends integrally above the active semiconductor area without overlapping part of the isolation region. The floating grid transistor is electrically isolated from the control grid by PN junctions that are inversely polarized.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种克服由其STI型隔离区域和其栅格材料之间的界面中存在的栅极电介质薄度引起的数据保持问题的存储器件。 解决方案：半导体存储器件包括具有单层栅格材料的非易失性可编程和电可擦除存储单元。 此外，存储单元包括浮动栅极晶体管和在有源半导体区域内的控制栅格，该有源半导体区域形成在衬底的区域中并由隔离区域限定。 其中形成浮栅的单层栅格材料在有源半导体区域上整体地延伸，而不与隔离区的重叠部分重叠。 浮栅晶体管通过PN极点与控制栅极电隔离，反向极化。 版权所有（C）2003，JPO

    4.
    发明专利
    未知

    公开(公告)号：FR2888660B1

    公开(公告)日：2007-10-05

    申请号：FR0507548

    申请日：2005-07-13

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE

    IPC: G11C7/14 ,  G11C11/14

    Abstract: The system has a memory controller interacting with an integrated circuit memory via a write bus, over which data is sent to a memory. A read bus outputs the data from the memory. The controller has a signal generating unit for generating a signal that is conveyed to read-out circuits of the memory in order to enable a column redundancy unit of memory subspaces, comprising a defective column address, via read-out circuits.

    Semiconductor device for electrically erasable and programmable read-only memory (EEPROM) with only one layer of gate material
    8.
    发明专利
    Semiconductor device for electrically erasable and programmable read-only memory (EEPROM) with only one layer of gate material 未知

    公开(公告)号：FR2838563A1

    公开(公告)日：2003-10-17

    申请号：FR0204690

    申请日：2002-04-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/02

    Abstract: The semiconductor memory device comprises a transistor with a floating gate (FG) and a control gate formed by the regions of source (S), drain (D) and channel of the transistor. The memory cell comprises a dielectric zone (ZTN) laid out between a first part (P1) of the layer of gate material and a first active zone (RG1) electrically insulated from a second active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate towards the first active zone at the time of erasing the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) extended between the first part and the ring gate. The first active zone (RG1) and the second active zone (RG2) are electrically insulated one from the other by the p-n junctions polarized in reverse, and on the surface by a region of shallow trench isolation (STI). The two regions of substrate (RG1,RG2) are of the first conductivity type, and the intermediate region (RG3) is of the second conductivity type. The isolation region (RG3) comprises an opening for a contact zone (PSB). The first region of substrate (RG1) comprises a contact zone (PC1) of the first conductivity type. The device also comprises the polarization means possessing the states of programming, reading and erasing the memory cell. The erasing of type Fowler-Nordheim is by applying a voltage to the first active zone much higher than to the regions of source, drain and substrate of the transistor. The programming is by hot carriers at the level of transistor. The programming of type Fowler-Nordheim is by applying to the region of source, drain and substrate the voltages much higher than to the first active zone. The device comprises a memory array incorporating several memory cells, where each memory cell is associated with an access transistor. An integrated circuit comprises the device as claimed.

    10.
    发明专利
    未知

    公开(公告)号：FR2812753B1

    公开(公告)日：2003-01-03

    申请号：FR0010287

    申请日：2000-08-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE

    IPC: H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  G11C11/40

    Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

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