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    Method for putting in waiting mode a component and associated integrated circuit
    32.
    发明专利
    Method for putting in waiting mode a component and associated integrated circuit 未知

    公开(公告)号：FR2838256A1

    公开(公告)日：2003-10-10

    申请号：FR0204303

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  LASSEUGUETTE JEAN ,  SCHOELLKOPF JEAN PIERRE

    IPC: H03K19/00 ,  H03K3/012

    Abstract: The component (C) comprises several complementary MOS transistors implemented or complementary substrates whereon the substrate potentials (VPWELL, VNWELL) are applied. The component (C) is put in waiting mode by decreasing the higher potential and increasing the lowre potential while the substrate potentials remain unchanged. The integrated circuit comprises the component (C), where the first potential of substrate (VDD0 or VSS0) is applied on a substrate of the first type component, and a potential limiter (R1) provides the component (C) as a substrate (VDD0 or VSS0), or the first limited potential (VDD1 or VSS1). The second potential of substrate (VSS0 or GND0) is applied to a substrate of the second type (p or n), and a potential limiter (R2) provides the supply potential (VSS or VDD), which is equal to the second potential of substrate (VSS0 or VDD0), or the second limited potential (VSS1 or VDD1). The potential limiter (R1) comprises a transistor (P0) whose source and substrate receive the first potential of substrate (VDD0), the gate receives a control signal (/REGUL) representative of the mode of functioning, and the first supply potential (VDD) is produced on the drain of the transistor; a transistor (N3) whose drain is connected to the source of the transistor (P0), and the source is connected to the gate by the intermediary of an inverter (11). The potential limiter (R2) comprises a transistor (N0) whose source and substrate receive the second potential of substrate (VSS0), the gate receives a control signal (REGUL), and the second supply potential (VSS) is produced on the drain of the transistor; and a transistor (P3) whose drain is connected to the source of the transistor (N0), and the source is connected to the gate by the intermediary of an inverter (I2).

    35.
    发明专利
    未知

    公开(公告)号：FR2787922A1

    公开(公告)日：2000-06-30

    申请号：FR9816582

    申请日：1998-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  SCHOELLKOPF JEAN PIERRE

    IPC: G11C11/404 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115

    Abstract: The proposed memory cell on the basis of complementary metal-oxide semiconductor (CMOS) technology comprises a capacitor (C) associated in series with an asymmetric programming transistor (T) having the drain region which is weakly doped and of greater thickness than that of the source (s). The series connection of the capacitor (C) and the transistor (T) is between terminals of a voltage supply, the positive voltage terminal (13) and the ground. The gate (g) of transistor (T) is connected for an input of the selection signal, and the capacitor (C) with terminals (1,2) is connected between the positive voltage terminal (13) and the drain of transistor. The first electrode (2) of the capacitor (C) is constituted by the drain region. The capacitor (C) is formed in an oxide layer constituting the gate of transistors. The second electrode (1) of the capacitor (C) is connected to the positive voltage terminal to receive in reading or decoding a relatively low potential (Vdd), and in programming a relatively high potential (Vprog). The transistor (T) and the capacitor (C) are dimensioned so that, in the course of a programming cycle and for a non-selected cell, the voltage of the capacitor remains below the breakdown voltage, when currents in the capacitor and the transistor are in balance. The transistor (T) is dimensioned to limit the current in the selected cell, which allows the breakdown in the oxide layer constituting the capacitor (C). The manufacturing process for the memory cell of anti fusible type employing the CmOS technology, consists in the formation of the regions of the drain of the asymmetric transistors with p-type conductivity channels, and simultaneously a well for receiving the MOS transistors with n-type conductivity channels. In an embodiment of the memory cell in an architecture with a stage for differential reading, the circuit comprises two proposed memory cells connected by two NMOS transistors to the same reading amplifier, which comprises two inverters in antiparallel connection and two output inverters.

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