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    1.
    发明专利
    未知

    公开(公告)号：FR2884968B1

    公开(公告)日：2007-09-21

    申请号：FR0503958

    申请日：2005-04-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHOELLKOPF JEAN PIERRE ,  ROCHE PHILIPPE ,  JAOUEN HERVE

    IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8244

    Abstract: The circuit has an intermediate layer (M0) placed between a surface (S0) of a substrate (100) and a metallization layer (M1), where the surface is covered by a stop layer (S10). Each of the intermediate, stop and metallization layers is constituted of two distinct dielectric materials in two zones, where the material in one zone presents a relative dielectric permittivity greater than that of the material in the other zone. An independent claim is also included for a method for fabricating an integrated electronic circuit.

    2.
    发明专利
    未知

    公开(公告)号：FR2871920B1

    公开(公告)日：2007-01-05

    申请号：FR0451190

    申请日：2004-06-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHOELLKOPF JEAN PIERRE

    IPC: G11C7/10 ,  G11C8/16 ,  G11C11/40 ,  G11C11/413

    Abstract: A storage circuit using a dual-access memory includes means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of activation of a given access. At least two successive activations of the means control operations of the same type, either reading or writing operations.

    4.
    发明专利
    未知

    公开(公告)号：FR2842351A1

    公开(公告)日：2004-01-16

    申请号：FR0208860

    申请日：2002-07-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHOELLKOPF JEAN PIERRE

    IPC: H01L23/525 ,  H01L21/71 ,  H01L23/58

    Abstract: The adaptation of an integrated circuit, made up of a pile of insulating layers (10, 14, 18) each with an associated level of metallisation forming electric contacts, to specific needs consists of: (a) forming some pairs of metallic regions (16A, 16B, 16C, 16D), the penultimate level of metallisation having a edge opposite and connected to the components of the integrated circuit; (b) depositing an insulating layer; (c) engraving, as a function of the specific needs, the insulating layer to expose the edges opposite determined pairs of metallic regions (16A, 16B); (d) forming metal portions (28A, 28B) of the final level of metallisation which covers the edges opposite the chosen pairs of metallic regions. An Independent claim is also included for an integrated circuit adapted to specific needs by this method.

    6.
    发明专利
    未知

    公开(公告)号：FR2787922B1

    公开(公告)日：2002-06-28

    申请号：FR9816582

    申请日：1998-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  SCHOELLKOPF JEAN PIERRE

    IPC: G11C11/404 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115

    Abstract: The proposed memory cell on the basis of complementary metal-oxide semiconductor (CMOS) technology comprises a capacitor (C) associated in series with an asymmetric programming transistor (T) having the drain region which is weakly doped and of greater thickness than that of the source (s). The series connection of the capacitor (C) and the transistor (T) is between terminals of a voltage supply, the positive voltage terminal (13) and the ground. The gate (g) of transistor (T) is connected for an input of the selection signal, and the capacitor (C) with terminals (1,2) is connected between the positive voltage terminal (13) and the drain of transistor. The first electrode (2) of the capacitor (C) is constituted by the drain region. The capacitor (C) is formed in an oxide layer constituting the gate of transistors. The second electrode (1) of the capacitor (C) is connected to the positive voltage terminal to receive in reading or decoding a relatively low potential (Vdd), and in programming a relatively high potential (Vprog). The transistor (T) and the capacitor (C) are dimensioned so that, in the course of a programming cycle and for a non-selected cell, the voltage of the capacitor remains below the breakdown voltage, when currents in the capacitor and the transistor are in balance. The transistor (T) is dimensioned to limit the current in the selected cell, which allows the breakdown in the oxide layer constituting the capacitor (C). The manufacturing process for the memory cell of anti fusible type employing the CmOS technology, consists in the formation of the regions of the drain of the asymmetric transistors with p-type conductivity channels, and simultaneously a well for receiving the MOS transistors with n-type conductivity channels. In an embodiment of the memory cell in an architecture with a stage for differential reading, the circuit comprises two proposed memory cells connected by two NMOS transistors to the same reading amplifier, which comprises two inverters in antiparallel connection and two output inverters.

    7.
    发明专利
    未知

    公开(公告)号：FR2787240A1

    公开(公告)日：2000-06-16

    申请号：FR9815769

    申请日：1998-12-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHOELLKOPF JEAN PIERRE ,  GAYET PHILIPPE

    IPC: H01L21/02 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/8239

    Abstract: Four transistors is formed in a semiconductor substrate and interconnected by a local interconnection layer (M0) situated under a first metallisation level (M1). Two resistances (LIL1,LIL2) provides local interconnection layer between the metallisation layer (M0) and the first metallisation level (M1). An Independent claim is included for: (a) a method of formation of integrated circuit disposed on two levels of metallisation

    DISPOSITIF DE MEMOIRE DU TYPE PROGRAMMABLE UNE FOIS, ET PROCEDE DE PROGRAMMATION
    8.
    发明专利
    DISPOSITIF DE MEMOIRE DU TYPE PROGRAMMABLE UNE FOIS, ET PROCEDE DE PROGRAMMATION 未知

    公开(公告)号：FR2884346A1

    公开(公告)日：2006-10-13

    申请号：FR0503571

    申请日：2005-04-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHOELLKOPF JEAN PIERRE

    IPC: G11C17/16 ,  H01L23/525

    Abstract: Chaque cellule-mémoire (CEL) comporte un transistor bipolaire (TR) enterré dans la première partie du substrat et une zone diélectrique (ZD) formée d'un matériau diélectrique capable d'être claqué de façon irréversible en présence d'une différence de tension de claquage qui lui est appliquée. Cette zone diélectrique est disposée au-dessus du substrat et possède une première surface en contact électrique avec une première électrode du transistor et une deuxième surface opposée à la première. Des moyens de programmation sont aptes à appliquer la différence de tension de claquage entre la deuxième surface de la zone diélectrique et l'électrode de commande du transistor de façon à rendre passante la jonction PN du transistor formée entre la première électrode et l'électrode de commande.

    9.
    发明专利
    未知

    公开(公告)号：FR2871282B1

    公开(公告)日：2006-09-15

    申请号：FR0406077

    申请日：2004-06-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHOELLKOPF JEAN PIERRE ,  FOURNEL RICHARD

    IPC: G11C17/08 ,  G11C17/16

    Abstract: A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

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