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    31.
    发明专利
    未知

    公开(公告)号：DE602005019069D1

    公开(公告)日：2010-03-11

    申请号：DE602005019069

    申请日：2005-11-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO

    IPC: G11C8/06 ,  G11C16/04 ,  G11C16/08

    Abstract: The invention relates to a method for accessing, in reading, programming and/or erasing, to a semiconductor integrated non volatile memory device of the Flash EEPROM type with a NAND architecture comprising at least one memory matrix (2) organised in rows or word lines (WL) and columns or bit lines (BL), and wherein, for the memory, a plurality of additional address pins are provided. Advantageously, the method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with said additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to said additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

    33.
    发明专利
    未知

    公开(公告)号：DE60226571D1

    公开(公告)日：2008-06-26

    申请号：DE60226571

    申请日：2002-02-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C11/56 ,  G11C16/04 ,  H01L21/28 ,  H01L29/792

    Abstract: An electrically-programmable memory cell programmed by means of injection of channel hot electrons into a charge-storage element (115a,115b;323) capacitively coupled to a memory cell channel (107;307) for modulating a conductivity thereof depending on a stored amount of charge. A first and a second spaced-apart electrode regions (109a,109b;309a,309b) are formed in a semiconductor layer (103;303) and define a channel region (107;307) there between; at least one (109A,109B;309B) of the first and second electrode regions acts as a programming electrode of the memory cell. A control electrode (CG) is capacitively coupled to the charge-storage element. The charge-storage element is placed over the channel to substantially extend from the first to the second electrode regions, and is separated from the channel region by a dielectric layer (1012,113;321). The dielectric layer has a reduced thickness in a portion (113;321b) thereof near the at least one programming electrode.

    35.
    发明专利
    未知

    公开(公告)号：DE69630678T2

    公开(公告)日：2004-09-23

    申请号：DE69630678

    申请日：1996-05-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/12 ,  G11C7/00

    Abstract: A column select multiplexer for a memory array organized in modules, each module handling two sets or bunches each of a certain minimum number of bitlines, is realized in a space opposite to the bitlines terminations and the select transistors are realized along a uninterrupted active area strip by realizing isolation gates between adjacent diffusions of two distinct select transistors. The bitlines of the two bunches handled by a multiplexer module are preferably interleaved and the respective select transistors are realized along two parallel uninterrupted active area strips.

    37.
    发明专利
    未知

    公开(公告)号：DE69630943D1

    公开(公告)日：2004-01-15

    申请号：DE69630943

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C16/26 ,  G11C16/32 ,  G11C16/06

    Abstract: The circuit (2) includes a memory element (33) connected to an enabling input (15) receiving an enabling signal (ATD), and in turn including a first reset circuit (45) receiving an internal reset signal (RES), and a second reset circuit (44) receiving an external timing control signal (OE), to generate an operating step enabling signal (PCn) having a first switching edge on receiving the enabling signal (ATD), a second switching edge on receiving the reset signal (RES), and a third switching edge on receiving the external timing control signal (OE). A control input (13) receives a timing mode signal (TLEV), and is connected to the first and second reset circuits (45, 44) to enable them selectively. By enabling the second reset circuit (44) and supplying the external timing control signal (OE), in successive cycles, with different delays in relation to the enabling signal (ATD), different readings of the memory are enabled to characterize the response and optimize the timing of the memory device.

    38.
    发明专利
    未知

    公开(公告)号：DE69630672D1

    公开(公告)日：2003-12-18

    申请号：DE69630672

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C16/28 ,  G11C16/06

    Abstract: A reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories, which comprises: a first branch for connecting a first load (1) and a memory cell matrix; a second branch for connecting a second load (1') and at least one virgin reference memory cell (4'); means (YM, YN) for selecting a memory cell (4) of the memory matrix; and means (YM, YN) for selecting at least one virgin reference cell (4'); each one of the first and second branches having a transistor (2, 2') for enabling the flow of current respectively between the first load (1) and the second load (1') and the memory cell matrix and the at least one reference memory cell (4'); the enabling transistors (2, 2') being controlled, respectively, by a first biasing structure (3) and by a second biasing structure (3'). The reference system has the particularity that it comprises at least one transistor (5) for redistributing the current of the load (1) on the first branch, which is connected in parallel to the enabling transistor (2), and a first equalization transistor (6) that is controlled by a precharge signal (PC) for the equalization of opposite nodes of the first and second branches; the at least one current redistribution transistor (5) provides a current imbalance in the first load (1) and in the second load (1') to sense the difference in conductivity between a memory cell (4) of the memory matrix and the at least one reference cell (4'), in order to determine the programmed or non-programmed status of the memory cell (4) of the memory matrix.

    39.
    发明专利
    未知

    公开(公告)号：DE69626815T2

    公开(公告)日：2003-12-11

    申请号：DE69626815

    申请日：1996-09-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/10 ,  G11C7/00

    Abstract: The invention relates to a control circuit (1) for an output buffer, of the type which comprises a first input terminal (I1) receiving a first enable signal (OEn) and a second input terminal (I2) receiving a second enable signal (CEn), as well as first (O1) and second (O2) output terminals to generate first (OE_L) and second (OE_H) partial enable signals to transfer discrete sets of data bits, the first (I1) and second (I2) input terminals being coupled to the first (O1) and second (O2) output terminals through a multiplexer (2), the control circuit (1) comprising a synchronization circuit (7) for linking the partial enable signals (OE_L,OE_H) operatively to a synchronization signal (SYNC) of the pulse type being synchronous with the loading of the output buffer, the synchronization circuit (7) being connected between an output terminal (O3) of said multiplexer (2) and the first (O1) and second (O2) output terminals of the control circuit (1).

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