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    33.
    发明公开
    "A reconfigurable control structure for CPUs and method of operating same" 审中-公开
    Eine rekonfigurierbare KontrollstrukturfürCPUs und eine Methodefürdessen Betrieb

    公开(公告)号：EP1408405A1

    公开(公告)日：2004-04-14

    申请号：EP02425620.8

    申请日：2002-10-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

    IPC: G06F9/30

    CPC classification number: G06F9/3885 ,  G06F9/30076 ,  G06F9/30181 ,  G06F9/3897

    Abstract: A reconfigurable control structure for CPUs comprises a first control unit (UC0) with a first basic instruction set associated thereto, and a second control unit (UC1), with a second instruction set associated thereto. Associated to the second control unit (UC1) is at least one programming element (MCP, MCS) for rendering said second instruction set selectively modifiable. Also present is at least one circuit element (IR, 10) for supplying instruction codes to be executed to said first control unit (UC0) and to said second control unit (UC1), so that each instruction can be executed under the control of at least one between said first control unit (UC0) or said second control unit (UC1) according to whether the instruction is comprised in the first basic instruction set and/or in the second selectively modifiable instruction set.

    Abstract translation: 寄存器（IR，10）向第一和第二控制单元（UC0，UC1）提供要执行的指令代码，使得每个指令可以根据每个指令是否包含在至少一个控制单元的控制下执行 基本指令集和可选择性修改的指令集之间的至少一个。 还包括使用控制结构的过程的独立权利要求。

    Method and circuit for calculating and storing the membership degrees of a fuzzy set
    35.
    发明公开
    Method and circuit for calculating and storing the membership degrees of a fuzzy set 有权
    方法和电路，用于计算并存储的模糊集合的隶属度

    公开(公告)号：EP1193645A1

    公开(公告)日：2002-04-03

    申请号：EP00830647.4

    申请日：2000-10-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pappalardo, Francesco ,  Giacalone, Biagio ,  Palano, Carmelo Marcello ,  Luzzi, Claudio ,  Grande, Francesca

    IPC: G06N7/04 ,  G06F1/035

    CPC classification number: G06F1/035 ,  G06N7/04

    Abstract: The invention relates to a codifying and storing method for membership functions (MF) representing a membership degree (α) of fuzzy variables (x) defined within a universe of discourse (U.d.D.) which is discretized into a finite number of points (n). The membership functions (MF) are quantized into a finite number of levels (p) corresponding to a finite number of membership degrees, and are stored by means of a characteristic value of each sub-set of values of fuzzy variables (x) having for their image the same value of the membership degree (α) corresponding to one of said levels.
    The invention further relates to a method for calculating the value of the membership degree of a fuzzy variable defined within a universe of discourse (U.d.D.) discretized into a finite number of points (n) with reference to a membership function (MF) thereof, as well as to a circuit (10) for calculating the membership degree (α) of a fuzzy variable (x) with reference to a membership function (MF) thereof.

    Abstract translation: 本发明涉及一种用于隶属函数表示话语的宇宙（U.d.D.）所有其离散成有限数目的节点（n）的内定义模糊变量（X）的隶属度（阿尔法）一个编纂和存储方法（MF）。 隶属函数（MF）被量化成对应于一个有限数目的隶属度的有限数量的水平（P），并且借助于每个子集的模糊变量值具有用于（X）的特性值的存储 其图像的隶属程度（阿尔法）相同的值对应于所述级别中的一个。 本发明还涉及到用于计算话语（UDD）的宇宙中定义的模糊变量的隶属度的值的方法参照隶属函数（MF）离散成有限数目的节点（n）的物， 以及为参照隶属函数（MF）其计算模糊变量（x）的隶属度（阿尔法）的电路（10）。

    Method and system for high-speed floating-point operations and related computer program product
    36.
    发明公开
    Method and system for high-speed floating-point operations and related computer program product 审中-公开
    Verfahren und SystemfürHochgeschwindigkeits-Gleitkommaoperationen undzugehörigesComputerprogrammprodukt

    公开(公告)号：EP1752872A2

    公开(公告)日：2007-02-14

    申请号：EP06116753.2

    申请日：2006-07-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

    IPC: G06F7/74

    CPC classification number: G06F7/74 ,  G06F7/485

    Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

    Abstract translation: 用于从包括实际加法输入或至少一个较早载入的操作数开始的加法器中估计传播载波的电路，该电路用独立的二进制数据对操作数执行统计电路操作。 优选地，该二进制流量是独立的和等能的或准等能的二进制流量，并且加法器是前导零预期逻辑整数加法器，产生与执行的整数相加结果相同数量的前导零的数字。 进位值可以由操作数的逻辑功能（例如，Karnaugh Map，Quine-McClusky）产生，作为覆盖逻辑功能中的所有1的操作数的逻辑组合。

    An improved cache memory system
    37.
    发明公开
    An improved cache memory system 有权
    Ein verbidityes Cache-Speicher系统

    公开(公告)号：EP1717708A1

    公开(公告)日：2006-11-02

    申请号：EP05103593.9

    申请日：2005-04-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

    IPC: G06F12/10

    CPC classification number: G06F12/0895 ,  G06F12/1063 ,  Y02D10/13

    Abstract: A cache memory system (115), comprising at least one cache memory (205) and a cache memory controller (210, Ft, Fd, 225, 230, 235, 245, 252). The at least one cache memory includes a plurality of storage locations (RLj), each one identified by a corresponding cache address (CADDR) and being adapted to store tag address portions (TAGi) and data words (DATi), each data word corresponding to a respective tag address portion. The cache memory controller is adapted to receive a first address (ADD) and to access the at least one cache memory based on the received first address.The cache memory controller includes a first address transformer (Ft, 225) adapted to receive the first address and to transform it into at least one first cache address corresponding thereto by applying a first transform function; the at least one first cache address is used by the cache memory controller for accessing the at least one cache memory to retrieve at least a first part of a tag address portion stored in at least one of the storage locations. The cache memory controller includes a hit detector (245) adapted to establish an at least partial hit condition based on a comparison of the retrieved at least a first part of the tag address portion and a first predetermined part (TAGp) of the first address, and a second address transformer (Fd, 225) adapted to receive the first address and to transform it into at least one second cache address corresponding thereto by applying a second transform function. The cache memory controller is further adapted to use the at least one second cache address for accessing the at least one cache memory to retrieve a data word corresponding to the retrieved tag address portion in case said at least partial hit condition is established.

    Abstract translation: 一种高速缓冲存储器系统（115），包括至少一个高速缓冲存储器（205）和高速缓冲存储器控制器（210，Ft，Fd，225,230,235,245,252）。 所述至少一个高速缓存存储器包括多个存储位置（RLj），每个存储位置（RLj）由相应的高速缓存地址（CADDR）标识，并且适于存储标签地址部分（TAGi）和数据字（DATi），每个数据字对应于 相应的标签地址部分。 高速缓冲存储器控制器适于接收第一地址（ADD）并且基于接收的第一地址访问至少一个高速缓存存储器。高速缓存存储器控制器包括适于接收第一地址的第一地址变换器（Ft，225） 并通过应用第一变换函数将其变换成与之对应的至少一个第一高速缓存地址; 所述至少一个第一高速缓存地址被所述高速缓冲存储器控制器用于访问所述至少一个高速缓冲存储器以检索存储在至少一个所述存储位置中的标签地址部分的至少第一部分。 高速缓冲存储器控制器包括命中检测器（245），其适于基于检索到的标签地址部分的至少第一部分与第一地址的第一预定部分（TAGp）的比较建立至少部分命中条件， 以及适于接收第一地址并通过应用第二变换函数将其变换成与其对应的至少一个第二高速缓存地址的第二地址变换器（Fd，225）。 高速缓冲存储器控制器还适于在建立所述至少部分命中条件的情况下，使用至少一个第二高速缓存地址来访问所述至少一个高速缓存存储器以检索对应于所检索的标签地址部分的数据字。

    Floating-point multiplication
    40.
    发明公开
    Floating-point multiplication 审中-公开
    浮点乘法

    公开(公告)号：EP1429239A3

    公开(公告)日：2006-06-14

    申请号：EP03027629.9

    申请日：2003-12-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pappalardo, Francesco ,  Visalli, Giuseppe

    IPC: G06F7/52 ,  G06F7/48

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49947

    Abstract: In a method for multiplication of floating-point real numbers (f, FN), encoded in a binary way in sign (SGN, SN), exponent (E, EN) and mantissa (M; MN), the multiplication of the mantissa (M; MN) envisages a step of calculation of partial products, which are constituted by a set of addenda (P) corresponding to said mantissa (MN). In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa (MN) to a value 1, in order to obtain a mantissa (MN) having a value comprised between 0.5 and 1.
    Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard.
    Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

    Abstract translation: 在用符号（SGN，SN），指数（E，EN）和尾数（M; MN）二进制编码的浮点实数（f，FN）相乘的方法中，尾数 M; MN）设想了计算部分产品的步骤，所述部分产品由对应于所述尾数（MN）的一组附加部分（P）构成。 为了减小为计算而设计的电路的尺寸和功耗，采用二进制编码的方法，其设想将尾数（MN）的第一位设置为值1，以便获得尾数（MN） 具有在0.5和1之间的值。还提出了用于实现乘法方法的乘积和电路的四舍五入方法。 还示出了根据IEEE754标准的用于从浮点实数转换到浮点实数编码的电路。 优先应用在便携式和/或无线电子设备中，例如移动电话和PDA，具有低功耗要求。

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