公开(公告)号：US09935184B2

公开(公告)日：2018-04-03

申请号：US14528338

申请日：2014-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungeun Byun ,  Jisoo Kyoung ,  Seongjun Park ,  Hyeonjin Shin ,  Hyunjae Song ,  Jaeho Lee

IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/66977 ,  H01L29/456 ,  H01L29/78

Abstract: An electronic device includes a semiconductor layer, a tunneling layer formed of a material including a two-dimensional (2D) material so as to directly contact a certain region of the semiconductor layer, and a metal layer formed on the tunneling layer.

公开(公告)号：US09721943B2

公开(公告)日：2017-08-01

申请号：US15052290

申请日：2016-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Keunwook Shin ,  Hyeonjin Shin ,  Seongjun Park ,  Hyunjae Song ,  Hyangsook Lee ,  Yeonchoo Cho

IPC: H01L23/528 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/53271 ,  H01L27/101 ,  H01L27/228

Abstract: A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two conductive material layers. The two-dimensional layered material layer may include a grain expander layer which causes grain size of a conductive material layer which is on the two-dimensional layered material layer to be increased. Increased grain size may result in resistance of the second conductive material layer to be reduced. As a result, the total resistance of the wiring structure may be reduced. The two-dimensional layered material layer may contribute to reducing a total thickness of the wiring structure. Thus, a low-resistance and high-performance wiring structure without an increase in a thickness thereof may be implemented.

公开(公告)号：US09595580B2

公开(公告)日：2017-03-14

申请号：US14508378

申请日：2014-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin Shin ,  Seongjun Park ,  Jaeho Lee ,  Jinseong Heo

IPC: H01L29/06 ,  H01L31/032 ,  H01L29/73 ,  H01L29/778 ,  H01L29/10 ,  H01L29/22 ,  H01L29/221 ,  C01B19/04 ,  C01G25/00 ,  C01G27/00 ,  C01G39/06 ,  C01G41/00 ,  H01L29/24 ,  H01L29/66 ,  H01L29/74 ,  H01L29/78 ,  H01L29/792 ,  H01L31/109 ,  H01L29/861 ,  H01L29/737 ,  H01L31/0352

CPC classification number: H01L29/0665 ,  C01B19/04 ,  C01G25/00 ,  C01G27/00 ,  C01G39/06 ,  C01G41/00 ,  C01P2004/20 ,  C01P2006/40 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/22 ,  H01L29/221 ,  H01L29/24 ,  H01L29/66977 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/737 ,  H01L29/74 ,  H01L29/778 ,  H01L29/78 ,  H01L29/792 ,  H01L29/861 ,  H01L29/8611 ,  H01L31/032 ,  H01L31/0322 ,  H01L31/0324 ,  H01L31/035281 ,  H01L31/109 ,  Y10T428/24802

Abstract: According to example embodiments, a two-dimensional (2D) material element may include a first 2D material and a second 2D material chemically bonded to each other. The first 2D material may include a first metal chalcogenide-based material. The second 2D material may include a second metal chalcogenide-based material. The second 2D material may be bonded to a side of the first 2D material. The 2D material element may have a PN junction structure. The 2D material element may include a plurality of 2D materials with different band gaps.

Abstract translation: 根据示例实施例，二维（2D）材料元件可以包括彼此化学键合的第一2D材料和第二2D材料。 第一2D材料可以包括基于硫族化物的第一金属材料。 第二2D材料可以包括第二金属硫族化物基材料。 第二2D材料可以结合到第一2D材料的一侧。 2D材料元件可以具有PN结结构。 2D材料元件可以包括具有不同带隙的多个2D材料。

公开(公告)号：US12272402B2

公开(公告)日：2025-04-08

申请号：US17708362

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Taein Kim ,  Youngtek Oh ,  Hyeonjin Shin ,  Changseok Lee

IPC: G11C16/04 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35

Abstract: Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

公开(公告)号：US12211904B2

公开(公告)日：2025-01-28

申请号：US17398515

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Minsu Seol ,  Hyeonsuk Shin ,  Hyeonjin Shin ,  Hyuntae Hwang ,  Changseok Lee ,  Seongin Yoon

IPC: H01L29/267 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/76

Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

公开(公告)号：US12211744B2

公开(公告)日：2025-01-28

申请号：US17552756

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Hyeonjin Shin ,  Alum Jung ,  Changseok Lee

IPC: H01L21/768 ,  C01B32/186 ,  C23C16/02 ,  C23C16/26 ,  C23C16/505 ,  C23C16/511 ,  H01L21/285 ,  H01L23/532

Abstract: A method of forming nanocrystalline graphene according to an embodiment may include: arranging a substrate having a pattern in a reaction chamber; injecting a reaction gas into the reaction chamber, where the reaction gas includes a carbon source gas, an inert gas, and a hydrogen gas that are mixed; generating a plasma of the reaction gas in the reaction chamber; and directly growing the nanocrystalline graphene on a surface of the pattern using the plasma of the reaction gas at a process temperature. The pattern may include a first material and the substrate may include a second material different from the first material.

公开(公告)号：US12139814B2

公开(公告)日：2024-11-12

申请号：US18298692

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok Lee ,  Hyeonsuk Shin ,  Hyeonjin Shin ,  Seokmo Hong ,  Minhyun Lee ,  Seunggeol Nam ,  Kyungyeol Ma

IPC: C30B29/38 ,  H01L21/02

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US12061312B2

公开(公告)日：2024-08-13

申请号：US17459537

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Choi ,  Hyeonjin Shin ,  Changseok Lee ,  Sangwon Kim

IPC: G02B1/113 ,  G02F1/1335 ,  G03F7/09 ,  H01L21/027 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/052 ,  H10K50/86

CPC classification number: G02B1/113 ,  G03F7/091 ,  H01L21/0276 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L31/02168 ,  H01L31/052 ,  H10K50/86 ,  G02F1/133502

Abstract: Provided are an amorphous boron nitride film and an anti-reflection coating structure including the amorphous boron nitride film. The amorphous boron nitride film has an amorphous structure including an sp3 hybrid bond and an sp2 hybrid bond, in which a ratio of the sp3 hybrid bond in the amorphous boron nitride film is less than about 20%.

公开(公告)号：US12046656B2

公开(公告)日：2024-07-23

申请号：US17405619

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonchoo Cho ,  Kyung-Eun Byun ,  Hyeonjin Shin

IPC: H01L29/45

CPC classification number: H01L29/45 ,  H01L29/452 ,  H01L29/456

Abstract: Disclosed is a semiconductor device including a surface-treated semiconductor layer. The semiconductor device includes a metal layer, a semiconductor layer electrically contacting the metal layer and having a surface treated with an element having an electron affinity of about 4 eV or greater, and a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure.

公开(公告)号：US12027588B2

公开(公告)日：2024-07-02

申请号：US18056446

申请日：2022-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/42364

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.